UFSOI: Process-Based Compact SOI MOSFET Models


Jerry G. Fossum, Mario M. Pelella, and Meng-Hsueh Chiang
Department of Electrical and Computer Engineering,
University of Florida, Gainesville, FL 32611, U.S.A.


SOI technology appears now to have become an advantageous, viable option for low-voltage and high-performance CMOS integrated circuits in digital, analog, and mixed-signal applications. The thin-film nature of the SOI MOSFET, however, can underlie physical mechanisms that complicate circuit simulation and portend equivocation in design. For example, floating-body (FB) effects [1], which in fact are obtained even in body-tied devices due to unavoidable high resistance [2], render empirical compact models like those used for designing bulk-Si CMOS circuits inadequate for reliable SOI circuit simulation. Furthermore, such models cannot be easily calibrated using common parameter-optimization techniques because of ambiguous data acquisition implied by SOI device self-heating in DC measurements and/or FB charge dynamics in pulse measurements designed to avoid self-heating; such optimization, because of the complex body charging dynamics, does not and cannot cover the large range of operational conditions that obtain in actual SOI CMOS circuits. Consequently, Silvaco has incorporated the physical process-based UFSOI MOSFET models [3] into SmartSpice and Utmost.


Model Description

The UFSOI implementation includes options for both the partially, or non-fully depleted (NFD) model [4] and the fully depleted (FD) model [5]. As illustrated by the network representation in Fig. 1, the models are charge-based with five terminals, and they have the FB option. The NFD model physically accounts for dynamic as well as DC FB effects in all regions of operation. The FD model physically accounts for the charge coupling between the front gate and back gate (substrate). Both compact models account for all the important features and mechanisms prevalent in scaled SOI MOSFETs, which include polysilicon-gate depletion, quantization due to quantum-mechanical carrier confinement, non-local carrier temperature-dependent impact-ionization current (I Gi ) [6] and velocity overshoot, and the parasitic bipolar transistor (BJT) currents and charges [7], which are properly coupled to the MOS currents and charges; the BJT base (body) current can comprise thermal generation, GIDL, junction tunneling, and impact-ionization currents. The noise (thermal, flicker, and shot) modeling accounts for hot-carrier effects on the channel thermal noise, important at high frequencies, and, with the implicit transimpedances, has been shown to predict the low-frequency Lorentzian excess noise component well [8]. The temperature modeling is truly physical [9], involving no extra parameters, and it is the basis of the self-heating option which uses a single-pole thermal subcircuit for each device. The FD model further accounts for the 2D source/drain field fringing in the back oxide (BOX), and the induced back-channel current (in weak/moderate inversion) [5]. The NFD model further accounts for nonuniform channel doping (e.g., via retrograde [4] and halo options), and its control of short-channel and parasitic BJT effects.

Figure 1. Network representation of the processed-based
UFSOI (NFD and FD) MOSFET models.


All currents and charges and their derivatives, which form the basis of the UFSOI quasi-static formalism, are continuous in all regions of operation [10]. The characterization of body charge (QB) in the FD model accounts for accumulation charge, which means that the model is hybrid-FD/NFD with regard to charge dynamics; in the FD (on) state, dQB /dt 0, which means that most FB effects are suppressed. In the NFD model, QB is defined by neutrality, which means that the charge dynamics properly reflects all the intrinsic transcapacitances. The FB effects are implicitly accounted for in the UFSOI models by proper merging of the carrier generation/recombination currents, the BJT and channel currents, and the charging, or transcapacitance currents. The merging, which is unified for DC, AC, or transient simulations, is reflected by the floating-body (B') nodal equation indicated in equation 1:

where neutrality implies


The combination of (1) and (2) defines VBS and VBD for any condition, and thereby describes how the intrinsic capacitive coupling and/or the recombination/generation in the device govern the FB effects as usually reflected by ICH (VBS ) and/or IBJT (VBS).

The truly physical nature of the UFSOI models renders their formalisms implicit, meaning that Newton-like iterative solutions have to be derived. Further, the derivatives (transconductances and transcapacitances) needed for the nodal analysis have been computed via difference approximations, necessitating five passes through the model routine for each call by SmartSpice. Recently, however, the use of approximate analytical derivatives for the NFD model in DC and transient simulations has been incorporated in UFSOI, with the exception the critical VBS -derivatives; difference approximations still have to be used in AC simulations. The result of this NFD speed-up is a physical yet computationally efficient model, requiring run-times that are not much longer than those required by empirical counterparts.


Process-Based Model Calibration and Utility

What makes the UFSOI models really unique, and, in our opinion, essential for reliable SOI circuit simulation, is their process basis. Key (~20) UFSOI model parameters are either structural or physics-based, and hence they are properly correlated and their evaluation can be done unequivocally in a straightforward manner, using device-structure data and measured data taken only in low-power regions where self-heating is negligible [11]. Such structure-dependent calibration renders the UFSOI models predictive, and useful for sensitivity analyses and next-generation performance projections [12], as well as reliable circuit simulation with devices in all possible regions of operation.

We exemplify this UFSOI utility by considering FB hysteresis in PD/SOI CMOS inverter-based circuits [13]. This hysteresis, first noted via UFSOI model predictions [14], is reflected by history-dependent propagation delays that are due to slow carrier recombination/generation processes superimposed on the fast body charge dynamics driven by the intrinsic capacitive coupling. The hysteresis is thus quite sensitive to the device structure as well as physics-based parameters such as carrier lifetimes. For example, Figure 2 shows a UFSOI-predicted ?fast? open-inverter-chain delay in time (from DC to the dynamic steady state) for L eff = 145nm PD/SOI CMOS for two different SOI film thicknesses (tSOI ). The "fast" delay is the one corresponding to initially (t = 0) body-charged (VDS =VDD = 1.8V VBS > 0 for the nMOSFETs, VBS < 0 for the pMOSFETs) active devices in the inverter chain; whereas the ?slow? delay would correspond to initially uncharged (VDS =0 VBS = 0) active devices. Note that reducing tSOI decreases the delay, but alters the hysteretic variation to an increasing delay with time. These results are due to the varying ratio of the gate-body capacitance to the drain-body capacitance, which increases with decreasing tSOI and tends to increase V BS (t). Thus, early in time, the "current overshoot" in the active device is enhanced; and later in time, a "dynamic strengthening" of the load device occurs. These results, which are consistent with experimental ones, clearly reflect the complexity of dynamic FB effects, and imply why a predictive (process-based) compact model is needed for reliable SOI circuit simulation.

Figure 2. Network representation of the process-based
UFSOI (NFD and FD) MOSFET models.



The process-based UFSOI models have been released to more than 100 companies and universities throughout the world, in addition to the SmartSpice releases. Both models are continually upgraded as the SOI technologies advance. In fact, the UFSOI/ NFD model is now being evolved into a unified process-based compact model for bulk-Si as well as PD/SOI MOSFETs; and the UFSOI/FD model is being upgraded for possible near-50nm node application and is the basis for a process-based model for double-gate MOSFETs now being developed at the University of Florida.



The development of UFSOI models at the University of Florida have been supported mainly by the Semiconductor Research Corporation. Many graduate students have made key contributions to the development over several years. The students include D. Chang, J. Y. Choi, L. Ge, K. Kim, H.-K. Lim, D. Suh, S. Veeraraghavan, G. O. Workman, and P. C. Yeh, in addition to coauthors Chiang and Pelella.



  1. S. Krishnan and J. G. Fossum, IEEE Circuits & Devices, vol. 14, p. 32, July 1998.
  2. G. O. Workman and J. G. Fossum, IEEE Trans. Electron Devices, vol. 45, p. 2138, Oct. 1998.
  3. J. G. Fossum, "UFSOI MOSFET Models (Ver. 5.0) User's Guide," SOI Group (http://www.soi.tec.ufl.edu), Univ. of Florida, Gainesville, Nov. 1999.
  4. D. Suh and J. G. Fossum, IEEE Trans. Electron Devices, vol. 42, p. 728, Apr. 1995.
  5. P. C. Yeh and J. G. Fossum, IEEE Trans. Electron Devices, vol. 42, p. 1605, Sept. 1995.
  6. S. Krishnan and J. G. Fossum, Solid-State Electron., vol. 39, p. 661, May 1996.
  7. S. Krishnan, Ph.D. Dissertation, Univ. of Florida, Gainesville, 1996.
  8. G. O. Workman and J. G. Fossum, IEEE Trans. Electron Devices, vol. 47, p. 1192, June 2000.
  9. G. O. Workman, J. G. Fossum, S. Krishnan, and M. M. Pelella, Jr., IEEE Trans. Electron Devices, vol. 45, p. 125, Jan. 1998.
  10. D. Chang, Ph.D. Dissertation, Univ. of Florida, Gainesville, 1997.
  11. M.-H. Chiang and J. G. Fossum, SOI Group Report, Univ. of Florida, Gainesville, Nov. 1998.
  12. M. M Pelella and J. G. Fossum, Preprint for IEEE Electron Device Lett., June 2000.
  13. M. M. Pelella, J. G. Fossum, M.-H. Chiang, G. O. Workman, and C. R. Tretz, Tech. Digest Internat. Electron Devices Meeting, p. 831, Dec. 1999.
  14. D. Suh and J. G. Fossum, Tech. Digest Internat. Electron Devices Meeting, p. 661, Dec. 1994.