Validation of CLEVER Interconnect Parasitics with 0.18 µm Process Measurements
Benoit Froment and Herve Jaouen - SGS-Thomson Microelectronics



CLEVER can perform accurate field solver extractions of resistance and capacitance from 3D structures generated from realistic process simulation. Comparison of CLEVER results with measurements made by SGS-Thomson Microelectronics were done to validate the simulator. Validation was done for a state-of-the-art process applicable to 0.18 µm technology. The process has the following features:

  • multiple dielectrics
  • conformal deposition around conductors
  • inter-metal fill with low-k dielectric
  • non rectangular metal cross sections

Process Description

The aim of the validation exercise is to make comparison of simulated and measured capacitances. To achieve this it is necessary to be very precise in the description of the process steps. The capacitances for deep sub-micron structures are highly dependent on process geometry especially for multi-dielectric technologies. CLEVER was used since it is designed to model interconnect parasitics by simulating the 3D back end process in a very accurate manner due to its advanced process models for photolithography deposition and etching [1].

The measurements and CLEVER simulations were carried out with the ST HCMOS7X process. The pitch is 1um and the part of SiO2 usually deposited by plasma (ECR), is replaced by a low-k material gapfill (Fox). The Fox thickness target is around 600nm. The permittivity of Fox deposited between metal line is around 3, whereas the dielectric constant of the TEOS capping layer is 4.2. However, there is a slight variation on these values due to the process dispersion. It is assumed that these fluctuations are under 5% of the initial value.

The process architecture for the metals 2, 3 and 4 is the same. The metal stack thickness (Ti + Al + TiN) target is 610nm. A TEOS liner of 50nm is deposited on the stack. In the two following steps, Fox and TEOS are deposited. After CMP, the capping layer thickness that remains on the Fox is around 900nm.

Figure 1. SEM of interconnect
cross-section for a low-k process.


Figure 2. CLEVER simulation of low-k process matched to SEM in Figure 1.



CLEVER Simulations

To be confident in reproducing the real process SEM photographs were used to optimize the process simulation steps. Based on these SEM observations it was possible to judge whether the simulation can be done using the faster Manhattan mode or more accurate Non-Manhattan mode (Figure 3). The tradeoff being to increase the speed of simulation.

Figure 3. Process simulation resulting in a
Non-Manhattan geometry of the metal 3 layer.

In addition the SEMs were able to show if during the process underetching or overetching occurred which can lead to a modification of width and space between materials. Adjustments can be made for this in CLEVER or through modifying the layout (Figure 4).

Figure 4. An example of a layout used for simulation.
Note the dimension of 100um * 50um.



Using a consistent methodology the simulation of 14 patterns was performed (Figure 4). In order to have the ability to vary some parameters during the simulation a parametrized input file was used (Figure 5). By using variable parameters in the input file it is possible to see the impact of the variation of the permittivity of the low-k dielectric, for example, on the capacitance in an simple way. To verify if the simulation result is quite similar to the real process the Ruler feature in TonyPlot was used to check thickness, space etc. (Figure 2).


Figure 5.An example input file to show parametrization
of input variables for easy experimentation.


Measurement Method Principle

ARPIC Method
Full details of the measurement system can be found in [2]. Different patterns coming from a technology independent environment called ARPIC are measured. ARPIC generator and circuit are described in the context of a 1606 interconnect patterns circuit implemented in a 6-metal layer, standard CMOS process with the use of a sub-femto-farad charged-based capacitance measurement (CBCM) driver. This matrix that contains the 1606 cells consists of 73 rows and 22 columns. Each cell includes two different capacitive loads and a driver.

One box contains the capacitances of the physical environment in which targeted capacitance will be measured (the context), and the other one contains the same environment capacitances plus the targeted capacitance (test pattern).

The original CBCM technique [3] is based on the assumption that non-selected patterns are not consuming current which is incorrect particularly with deep submicron technologies. A parasitic current due not only to Miller effect on switching transistors but also to static current is measured for each die in pattern characterization conditions but without any pattern selected, is indeed observed and must be subtracted from the values.

Resolution Evaluation
Assuming that the capacitance of the common part of the cell is the same in the context and test pattern cases, a differential term is obtained that is assumed to be due to the test structure under consideration. This approximation represents the main limitation of the measurement resolution.

Mismatch in the MOS transistor in metal lines and all asymmetries in layout can damage the resolution of the method. To evaluate those mismatches, matching patterns have been disseminated among the matrix. In those patterns, interconnect capacitance is the same on the context and test patterns. Some matching patterns are empty, which means that the capacitances read on the context and test pattern are due to upper mismatch. Those values are then subtracted to those read on the two patterns during characterization. There are only a few patterns spread out in the matrix array. So if the empty pattern is spaced out from the measured pattern the value subtracted is not always relevant. Therefore considering the distribution of empty patterns values, we can reasonably assert that the resolution capability of the method is between 0.2fF and 1 fF depending on empty pattern value (process dispersion) and on the distance between pattern and empty one. If we only consider the best dies, we can assert that the resolution capability of the method is below 0.5 fF. The capacitances measured range from 1 to 50 fF, Vdd = 2.5V. Two frequencies were used : 1Mhz and 80Mhz. For f = 80Mhz, a 1 uA current means a 5 fF capacitance.

Method limitation
The differential term does not represent a term of the capacitance matrix defined for a particular system of electrodes, since there is only one net that receives the signal Vdd. The other ones are all grounded. The capacitances measured in each half-cell are described later for each case. This example means that the difference term does not represent C12. The result has no real physical significance as far as capacitances are concerned (unless C12 >> C10 - C20). However, even if the ARPIC result has no direct physical meaning, it still can be used to calibrate the simulator. The two cells, context and test pattern, have to be simulated, and then subtracted.


Experimental Description

The comparison between simulation and measurements is done on 14 different quasi-2D patterns. Results are shown 6, 7 and 8. The physical slice of 3D-patterns composed for example of two crossing lines, is very difficult : two perpendicular slices have to be done on the same pattern to note the elementary dimensions (oxide and metal thickness, metal width, etc.).

The 14 patterns can be divided into three groups:

A: FM3 (Fringe Metal 3) : two parallel lines of a 0.6µm length in metal 3, are separated by 5 different spaces.
The results are shown in Figure 6.

This configuration permits analysis of the cross talk phenomena. Another interest is to see the advantage brought
by the low-k dielectric material, Pox, substituted for Si02, on the intra-metal-capacitance.


B: FM3M4 (Fringe Metal 3 Metal 4) : two parallel lines of a 0.6um width and a 100um length with one line made of
metal 3 and the other one of metal 4. The space between line has also 5 different values : s = 0.4µ, This configuration
could put forward how edge effects are taken into account by CLEVER. Results are in Figure 7.

C: PM3M4 (Plane Metal 3 Metal 4) : one plate of metal 3 is below a plate of metal 4 with no overhang (the 2 plates have
the same width and are parallel). The length is 100um again. W takes 4 different values : 0.6µm, 0.8µm, 1.4µm, 5µm.
Results are in Figure 8.


Validation Summary

Figures 6, 7 and 8 show the comparison of measured and simulated results for the three patterns described above. All results show good matches. Most are well within the limitations of the measurement resolution.


Figure 6. Comparison between simulation ( ) and measurements ( ) for lateral capacitance.
Two parallel lines of metal 3 of 0.6um width and 100 um length.


Figure 7. Comparison between simulation ( ) and measurements ( ) or different
layer fringe or edge capacitance. Two parallel lines of 0.6um width and 100 um
length with one line in metal 3 and the other of metal 4.


Figure 8. Comparison between simulation ( ) and measurements ( ) for two stacked lines.
Two parallel lines of metal 3 and metal 4 without any overhang.


CLEVER has been demonstrated to model accurate interconnect parasitics for a state-of-the-art metal process featuring conformally deposited barrier materials around non-rectangular metal lines and low-k dielectric fillers.

For LPE rule like generation using the same accuracy, EXACT can be used since it is using the common 3D process simulation techniques.



  1. Simulating Accurate 3D Geometries for Interconnect Parasitic Extraction using CLEVER.
    Simulation Standard August 98.
  2. Interconnect Characterization" Interconnect Characterization"
  3. J. Chen. "An on-chip, interconnect capacitance characterization method with sub-femto-farad
    resolution", ICMS March 97.