Cell Characterization with .MODIF Statement
in SmartSpice


SmartSpice provides many unique and powerful features to facilitate parametric analysis in general and cell characterization in particular. As discussed in [1], a typical use of these features is in the generation of lookup tables for timing tools, such as those provided by Synopsys. These tables relate propogation and delay times to variations in parameters such as input transition times and load capacitance values. The features of SmartSpice that are most applicable to this form of analysis are the .MODIF and .MEASURE statements.

Another form of characterization that is particularly important is the computation of setup and hold time for sequential circuits. These calculations are more difficult than standard parameter sweeps and require some additional features of the .MODIF statement and of the SmartSpice command processor, to maximize the efficiency of these simulations. This article will focus on the efficient use of the .MODIF statement when applied to the problem of cell characterization.

.MODIF Statement

The .MODIF statement is the most flexible and powerful statement for parametric analysis and optimization in SmartSpice. In its most simple form it allows the user to simultaneously modify any number of parameters in the input file. Parameters that can be modified include device parameters, model parameters, parameter labels (.PARAM) and temperature. Parameter variations can be expressed as constant increments (+= and -=) or multipliers (*= and /=) of an initial value, lists of possible values or statistical distributions.

The .MODIF statement can have multiple sets of parameter variation, with each set being separated using the MODIF keyword. An example of a .MODIF statement with two sets is shown in Example 1.

  .MODIF LOOP = 5 
  + temp = 100
  + cload(cap) = 1.2p
  + rise_time += (0.5n) 0.1n
  + MODIF LOOP = 5
  + cload(cap) = list( 0.5p 0.7p 1.0p 1.2p 1.5p )

Example 1: .MODIF statement with multiple simulation sets.

In this example 5 simulations will first be run with temperature and load capacitance held constant, and 'rise_time' swept from 0.5ns in increments of 0.1ns. Once the 5 simulations are completed the next set will be executed. Parameters will retain the final value from the previous set of simulations, unless the new set explicitly changes the value. For example, during the second set of simulations, the temperature will be 100oC and 'rise_time' will be 0.9ns. The value of the load capacitance will be swept using the supplied list of values. Hence, a total of 10 simulations will be executed.

In the previous example each MODIF set executes a fixed number of simulations, i.e. the stop criteria for the loop is specified using the LOOP keyword. For any MODIF set, it is possible to also specify a conditional stop criteria as a function of a particular measurement in the circuit. This is particularly useful if a circuit will succeed for some initial values of parameter, but eventually fail to behave correctly for a particular parameter value. Since the value at which this will occur is unknown to the user, use of a conditional stop can significantly reduce simulation time by stopping simulation after the first failure, and ignoring the remaining redundant simulations. An example of a .MODIF analysis with a conditional stop is given in Example 2.

  .MODIF LOOP = 20 STOP del_rise LE 1.1n
  + rise_time = 0.5ns
  + cload(cap) += (0.1pF) 0.2pF

Example 2: .MODIF statement with conditional stop.

In this example 'del_rise' is a measurement performed after a simulation. A maximum of twenty simulations (LOOP = 20) will be performed, with the load capacitance swept from 0.1pF in increments of 0.2pF. SmartSpice will interrupt this MODIF set once twenty simulations have been performed OR the value of the 'del_rise' measurement is less that or equal to 1.1ns. The conditional stop is set by the "STOP del_rise LE 1.1n" portion of the statement.

Once simulation of a particular MODIF set is interrupted, SmartSpice will move to the next set if it exists or move to the next stage of simulation. Each MODIF set can contain both absolute and conditional stop criteria. By combining conditional stops with multiple MODIF sets, it is possible to create a very efficient method of characterizing setup/hold time.

Setup and Hold Time Computation

The setup time of a circuit is defined as the minimum time prior to some event, usually a clock edge, that an input to the circuit must remain stable to ensure reliable device operation. The hold time is defined as the time that the input must remain stable after the event.

The typical approach taken to characterize the setup time is shown is Figure 1. A clock edge is generated at the time Tck, and the input node changes value at the time Tin. Initially Tin is such that the output of the cell performs as expected. Then Tin is incremented by the required resolution of the eventual solution until a stop value is reached. The setup time is then taken as the Tck - Tin for the last valid simulation.


Figure 1. Typical approach taken to determine setup time.



In an input deck, this can be achieved in a number of different ways. Example 3(b) shows the use of a nested transient sweep and Example 3(c) shows the use of a .MODIF analysis. Example 3(a) shows the definition of the input and clock pulses, with the measurement of the maximum output voltage and the difference between the edge of both pulses.

	.PARAM tck=10n tin=7n
	Vck ck 0 pulse 0.0 3.3 'tck' 1n 1n 100n
	Vd  d  0 pulse 0.0 3.3 'tin' 1n 1n 100n
	.MEASURE max_q MAX v(q)
	.MEASURE setup TRIG v(d) RISE=1 VAL=1.6 
	+	TARG v(ck) RISE=1 VAL=1.6 
	.MEASURE tpd 	TRIG v(d) RISE=1 VAL=1.6 
	+	TARG v(q)  RISE=1 VAL=1.6
  .TRAN 0.01n 20n SWEEP tin 7n 10n 0.1n
	.TRAN 0.01n 20n
  + tin += (7n) 0.1n


Example 3: a) Portion of input netlist, b) Nested transient sweep, c) .MODIF implementation of nested transient sweep in b).

As can be seen in this example, 31 simulations will be required to compute the setup time to a resolution of 0.1ns. Depending upon the cell being characterized, this approach can result in many of the simulations failing. For example if the setup time is 1ns, then all simulations with 'tin' > 9ns will fail.

To increase the efficiency of the characterization, it is possible to use a conditional stop to prevent unnecessary simulations taking place. Typically the cell is taken to fail if the output voltage fails to pass a certain threshold value. If the maximum or minimum value of the output voltage is measured, this can be used in the stop condition, as shown in Example 4.

  .MODIF LOOP=31 STOP max_q LE 1.6
  + tin += (7n) 0.1n

Example 4: Use of .MODIF to reduce number of simulations.

In this example, up to 31 simulation could be performed, however only one simulation that fails will be performed. Hence, if the setup time is 1ns, ~10 simulation can be skipped. This can result is significant time savings, especially if the AUTOSTOP option is being used to halt simulation once all measurements are complete. Simulations that fail will simulate up to the final time, i.e. 20ns, while simulations that succeed will typically only need to be simulated up to ~12n (depending on propogation delay and output rise time).


Binary Search Method

The problem of calculation of the setup/hold time of a circuit is similar to the problem of searching for an element in an already sorted set. A binary search is much faster and consequently more efficient than a standard linear search. This technique can also be applied to the search for a setup/hold time and can be accomplished through use of multiple MODIF sets and conditional stops. This technique is illustrated in Example 5.

  .MODIF LOOP=4 STOP max_q LE 1.6
  + tin += (7n) 1n
  +MODIF LOOP=2 STOP 1.6 LE max_q
  + tin -= 0.5n
  +MODIF LOOP=2 STOP max_q LE 1.6
  + tin += 0.25n 
  +MODIF LOOP=3 STOP 1.6 LE max_q 
  + tin -= 0.1n

Example 5: Binary search of setup time using .MODIF.

In this example, 'tin' is initially incremented in 1ns steps until the circuit fails. When this happens the second MODIF set will decrement 'tin' in 0.5ns intervals until the output voltage is again greater than 1.6V. At this stage the setup time has been calculated to a accuracy of 0.5ns. To get to the required resolution of 0.1ns, two more MODIF sets are used, with steps in 'tin' of 0.25ns and 0.1ns respectively.

This approach results in a calculation of the setup time to the required accuracy in a worst case of 8 simulations, as compared to the original 31 simulations. To increase the resolution by a factor of 2, only 1 more simulation is needed, whereas with the linear search, 31 more simulations are needed.


This article has discussed the use of the .MODIF statement in the characterization of cells. This statement can greatly increase the efficiency of characterization by reducing the number of simulations required and performing all characterization stages within one process. In a future article, some more advanced uses of the MODIF statement in combination with the SmartSpice command interpreter will be discussed.