Simulating Accurate 3D Geometries for Interconnect Parasitic Extraction Using CLEVER



CLEVER is designed to model interconnect parasitics by simulating the back end processing steps of custom cells in three dimensions. A 3D process simulator is used to realisticly reproduce the effects of photolithography, deposition and etching on the resulting structure topography. Geometric etches and depositions are also possible to increase the speed of simulation if required. The process steps are driven from existing masks in standard GDSII data format from the actual design, or the mask set may be created using MaskViews . The 3D grid re-meshing required for each of the steps is generated totally automatically and requires no user input. This feature makes the whole package exceptionally easy to use, even for those unfamiliar with process simulation. Figure 1 shows an SRAM cell geometry during processing. Effects of lithography on the metal 1 layer are seen.

Figure 1. 3D selection of an SRAM cell after metal 1 lithography
and etch. Accurate description of the as-processed geometry is
required for correct parasitic extraction.


Interconnect Analysis

Once all the process steps have been simulated, the addition of the following single line to the input file:

Interconnect Capacitance Adapt

will initiate the integral 3D field solver in CLEVER to calculate the capacitance matrix between each conductor and every other conductor and between each conductor and the substrate. This will create an accurate netlist of the parasitic capacitive loading effect on each node for SPICE circuit simulation. The analogous command:

Interconnect Resistance Adapt

will calculate a SPICE netlist of the parasitic resistance of each of the tracks between each node. The effects of using realistic 3D process simulation on the electrical timing characteristics of logic cells has been discussed previously, in the June 1997 issue of "Simulation Standard". In this article, we focus on some of the 3D processing capabilities of CLEVER that are more advanced and were therefore not described before. Here the ease of creating an realistic input file is also emphasized.


Simulating Local Oxidation

Although not strictly considered as "back end" processing, the capability to simulate a standard LOCOS structure available. This example is shown to demonstrate the ease of use of the program and how it closely resembles a real process flow. The complete input file shown in Figure 2 is all that is required to create a LOCOS structure example using Silvaco's 3D process simulator.

Figure 2: An Example Input File to Create a 3D LOCOS Structure


A description of the input file is as follows: Firstly ODIN the 3D process simulator used by CLEVER is called by the "go odin" statement. Next the group of layout masks called "mask.lay" is used to initiate the size of the starting substrate. The "Depth" parameter defines the thickness of the substrate and the "padding" parameter tells the simulator to increase the area simulated by an additional 3um around the edge of the masks. Incidentally, all references to thickness are in microns.

The following "Deposit", "Etch" and "Strip" statements are self explanatory. The "Mask" statement tells the simulator to deposit photo resist, and develop a pattern defined by the mask called "LOCOS". After etching the nitride, stripping the resist and oxidizing, the 3D structure is then saved in a structure file called "LOCOS_3D.str" and can be plotted using the 3D graphics package TonyPlot3d.

Notice that there is no reference at any time to the creation or definition of the three dimensional grid required for the process simulation. All of this is taken care of and is invisible to the user. The user can, of course, plot the grid that has been created, as well as any of the other parameters, using TonyPlot3d.


Defining Two Dimensional Cutlines

Although designed as a 3D simulator, CLEVER can be used in 2D mode (or even 1D mode ) by defining a cutline through the mask set. All the advantages of automatic grid definition and ease of input syntax are retained if the process is run in two dimensional mode. Obviously the bonus of 2D simulation is a huge increase in simulation speed.

Using the input file in figure 2 as an example, if the syntax below is added to the end of the input file above, the simulator makes a cutline through the mask set at a location defined (X1, Y1, X2, Y2), saves a structure file and plots the result using the 2D graphics package, TonyPlot.

Cut line=(0, 5, 10, 5)

Save Structure="LOCOS_2D.str"

tonyplot LOCOS_2D.str

Once again, notice the ease of creating the input file and the intuitive command language that is used. The result of this simulation is shown in Figure 3.

Figure 3. Showing a cutline through the 3D LOCOS structure generated in CLEVER.


3D Modeling of Local Interconnect

Now that a LOCOS structure is created, the processing sequence may be continued to create a further example structure with a local interconnect. This allows the study of the parasitic local interconnect resistance variations with different geometries and thicknesses. The mask layers for the various process steps were created using MaskViews and are shown in Figure 4.

Figure 4. Showing the masks made using MaskViews required to
generate the 3D Local-Interconnect structure.



The simulation begins by loading in the 3D LOCOS structure that was created in the previous example, depositing poly, then a thin layer of oxide, etching contact holes for the local interconnect and then depositing and defining the local interconnect material. This is followed by traditional back end processing consisting of bpsg deposition, etching and aluminum deposition. The example input file is shown in Figure 5.

Figure 5. Example Input File to Create a MOSFET with Local Interconnect


In this part of the input file, instead of simple deposit statements, the physical deposit model is automatically called by specifying a deposit rate and time. Realistic photolithography and etching models can also be called by using similar syntax in the input file for these processes. The final structure is shown in Figure 6 with the oxide layer removed for clarity. A 2D cutline of the same structure near the local interconnect is shown in Figure 7.

Figure 6. Graphics from TonyPlot3D showing the local
interconnect bridging the polygate and service contacts.


Figure 7. 2D cutline generated by TonyPlot3D showing section
through the 3D structure near the local interconnect.



A further feature demonstrated in this input file is the "Reverse" parameter in the "Mask" statement. The "Reverse" parameter reverses a mask from dark field to light field or vice versa. In processing terms, this has the same effect as using negative resist as opposed to the default positive resist. This feature is useful when designing masks for certain processes such as via etches in the oxide, where it is easier and more useful to draw and visualize where the contact holes are, rather than draw a mostly dark field mask.

At the end of the process simulation, the conductivity of the TiN interconnect material is defined. This conductivity number should be extracted from test structures on the wafer for an individual process. The "Interconnect Resistance Adapt" command calculates the resistance of all conducting tracks between each node and forms a resistance matrix for inclusion in a file as a SPICE netlist. This is saved as a file in the last line of the input file.


Using the Simple Deposit Statement to Simulate a Damascene Structure

The final example shows how a simple deposit statement, using one of the geometric model options, can simulate a deposition followed by Chemical Mechanical Polishing (CMP). It also demonstrates performing a whole process simulation in two dimensions which takes only a few seconds of run time. The input file is shown in Figure 8.

Figure 8. Low k dielectric in-fill Damascene type structure
generated using simple process commands.


The meaning of the initial statements has already been described. For geometrical depositions, there are three options, namely "Max", "Min" and"Conformal", the default setting being "Max". If the parameter "Max" is added to the "Deposit" statement, the deposited thickness will be measured from the highest point on the present structure, and the deposit will fill all voids below this height. This has the effect of deposition and planarization in one deposit statement. The effect is shown in Figure 8, where it can be seen that"LoK" material appears as a deposited and polished (planarized) film.

The other geometrical options on the deposit statement are "Min" and "Conformal". The "Min" statement is similar to the "Max" statement except that the deposited thickness is measured from the lowest height of any part of the structure. Conformal is the more typical deposit statement and deposits a uniform thickness of material which follows the contours of the structure.

After the structure has been simulated, the "Interconnect Capacitance Adapt"command calculates the capacitance matrix which is then saved as a SPICE netlist.

Figure 9. 2D cross-section of a low k di-electric fill process.
Correct handling of the inter metal geometry is required
to obtain accurate lateral capacitance.



Various 3D process simulation features in CLEVER have been demonstrated with actual input files. These include the formation of LOCOS and local interconnect structures together with the three versatile options available using geometrical deposition. It has been shown that the cutline feature allows the 3D process simulation to be reduced to a 2D simulation at any point in the simulation. The ease of using physical models has also been demonstrated. The physical models available include photoresist development,film deposition and etching. An oxide growth model is also incorporated into the code.

The examples show how to define material properties such as resistivity and permittivity and how to implement the resistance and capacitance matricies calculation for inclusion into a SPICE netlist for circuit simulation. These input files are designed to show the ease of use of the program, in particular,the complete absence of any mesh definition requirement as a result of the automatic 3D mesh generation and adaption facility.