RPI* Polysilicon and Amorphous TFT Implemented in SmartSpice


Modified crystalline MOSFET models have been widely used to describe the characteristics of polysilicon and amorphous thin film transistors (TFTs). However, these models are not capable of reproducing the localized state effects in TFTs. The localized states cause the kink effect in polysilicon TFTs and affect threshold voltage, the field-effect mobility, the subthreshold/leakage currents and the frequency dispersion of the capacitance in both a-Si:H and polysilicon TFTs.

Accurately modeling these effects becomes increasingly important as the device dimensions are scaled down and design margins are reduced. TFT models that satisfy the above requirements have been developed by the Center for Integrated Electronics and Electronics Manufacturing at Rensselaer Polytechnic Institute[1,2]. The physically based analytical TFT models are fully scalable " with device geometry Model parameters can be easily extracted using UTMOST.


In the crystalline silicon device, the knee of the log(Id)-Vgs curve is very sharp, and the Id-Vgs characteristic quickly becomes linear. The result is that the threshold voltage (Vt) and the on voltage (Von) of the device are nearly equal. In contrast, the Von is larger than Vt in the non-crystalline transistor due to the bandgap states. This results in a comparatively small current at threshold and the current transition from the the exponential to the linear regine is much more gradual. In addition to the leakage, subthreshold, and above threshold conduction regimes, the polysilicon model also covers the kink regime. The kink effect in polysilicon TFT occurs at large biases when the TFT is in saturation. Electron-hole pairs generated through impact ionization recombine in the channel via boundary trap states and the feedback is caused by the recombination. The feedback effect does not occur and therefore the current increase is not nearly as dramatic in crystalline silicon transistors. The non-crystalline effects have been currently modeled in the Rensselaer TFT models.

The Rensselaer TFTs models have the following features:

  • Universal charge control model, which guarantees stability and conversion
  • AC models accurately reproduces Cgc frequency dispersion
  • Temperature dependence included
  • Automatic scaling of model parameters to accurately model a wide range of device geometries
  • A minimum number of physically based parameters that can easily be extracted from experimental data and related back to the fabrication steps
  • Verified using a wide variety of TFT structures from many foundries


In addition, the a-Si:H TFT model uses a unified Ids equation which covers all regimes of transistor operation. Therefore, the derived conductance gds and gm have no discontinuity problems through the regime boundaries.

Both of these models are implemented in SmartSpice and are be available on Unix or PC.

Figure 1. A typival Ids vs VDS simulation data using the RPI TFT model.




The TFT models described in this article were developed by the Semiconductor Devices Research Group at RPI, under the direction of Professor Michael Shur. Silvaco would like to acknowledge RPI's contribution of model code and documentation, which greatly facilitated implementation of these models within SmartSpice.


[1.] Michael S. Shur, H. C. Slade, et al, "Modeling and scaling of a-Si:H and Poly-Si Thin film transistors", MRS Spring Meeting, San Francisco, March 31 - April 4, 1997.
[2.] Michael S. Shur, Mark D. Jacunski, et al.,"SPICE models for amorphous silicon and polysilicon thin film transistors", Elec.Chem. Soc. Proc., Vol 96-23, p242-259, 1996.