BSIM3v3.1 Intrinsic Capacitance Modeling in UTMOST


The "INT.CAP" routine is now available in MOS technology of UTMOST as part of the capacitance measurement module. The "Intrinsic Cap." routine can be used to measure overlap caps, channel capacitance and total gate capacitance. The routine also includes the automatic extraction of BSIM3V3 capacitance parameters and simulation/optimization capabilities using SPICE.


Hardware Configuration

The "INT.CAP" routine allows users to apply external DC bias to the MOS device during the CV measurements. UTMOST controls the DC analyzer and the LCR meter concurrently. The user should select the proper DC analyzer and the LCR meter from the Hardware Configuration screen (Figure 1) and complete the terminal connections before starting the "INT.CAP" routine.

Figure 1. Hardware configuration screen.


It is recommended to have a large W MOS device (W > 500 µm) for the "INT. CAP" routine measurements. If the W is not large enough the parasitic caps associated with the setup can effect the accuracy of the measurements (Even after the calibration is performed).


Measurement Setup

The "INT.CAP" routine is in the "CAP" analysis section of the UTMOST MOS technology. Open the "Setup and Result" screen and toggle the "Routine Pointer"button until it reads "CAP". The "INT.CAP" routine will appear as routine #67 (Figure 2).

Figure 2. INT.CAP routine in setup screen.


In order to set the bias conditions select the "INT.CAP" routine and press the "Set Measurement" button. This will open the "Capacitance Measurement Screen". (Figure 3.)


Figure 3. Capacitance Measurement
Screen for the "INT.CAP" routine.


The "c_start_bias", c_stop_bias" and "c_step_bias" measurement variables are belong to the LCR meter's internal DC sweep and they are shared by all types of capacitance measurements performed in the "INTCAP" routine. The remaining DC bias conditions belong to the DC analyzer and they are specific to the capacitance measurement type.

Capacitance measurements offered by the "INT.CAP" routine:

CGS : Gate to source capacitance

CGD : Gate to drain capacitance

CGC : Gate to channel capacitance

CGB : Gate to bulk capacitance

CGG : Total gate capacitance

In addition to the listed measurements there is an intrinsic capacitance simulation capability which simulates the nine intrinsic capacitances together.

Selection of the type of capacitance measurement can be done by pressing the "Multiple Select." button in the "Routine Control Screen".This will open the "Multiple Routine Screen" and the capacitance measurement types will be listed (Figure 4). The buttons in the"Multiple Routine Screen" can be toggled. The selected measurements types will have the red color.


Bias Settings:

Below is the description of the measurement variables used in the "INT.CAP"routine setup screen (Figure 4.) :

VD_start_cgs: VD (drain voltage) start bias (supplied by DC analyzer) for CGS measurements. Also used as the VD value for "Simulation Only" Intrinsic caps.
VD_step_cgs: VD (drain voltage) step bias (supplied by DC analyzer) for CGS measurements.
#of_step_cgs: Number of VD steps for CGS measurements.
VS_start_cgd: VS (source voltage) start bias (supplied by DC analyzer) for CGD measurements.
VS_step_cgd: VS (source voltage) step bias (supplied by DC analyzer) for CGD measurements.
#of_step_cgd: Number of VS steps for CGD measurements.
VB_start_cgc: VB (bulk voltage) start bias (supplied by DC analyzer) for CGC measurements.
VB_step_cgc: VB (bulk voltage) step bias (supplied by DC analyzer) for CGC measurements.#of_step_cgc : Number of VB steps for CGC measurements.
VD_start_cgb: VD (drain voltage) start bias (supplied by DC analyzer) for CGB measurements.
VD_step_cgb: VD (drain voltage) step bias (supplied by DC analyzer) for CGB measurements.
#of_step_cgb: Number of VD steps for CGB measurements.
c_start_bias: Starting DC bias voltage for the LCR meter sweep.
c_stop_bias: Stop DC bias voltage for the LCR meter sweep.
c_step_bias: Step bias voltage for the LCR meter sweep.




Figure 4 "Multiple Routine
Screen" of the "INT.CAP" routine.



Terminal Connections for the "INT.CAP" Measurements

The "INT.CAP" routine allows users to measure various MOS capacitances while the device is under DC bias and conducting current. This requires the DC analyzer and the LCR meter to work jointly. The terminal connections also become an important issue due to the AC and DC current paths which define the total measured capacitance. The following are the terminal connections which are needed for the different types of capacitance measurements available in the "INT. CAP" routine.

CGS measurement connection


CGD measurement connection


CGC measurement connection


CGB measurement connection


CGG measurement connection


Measurement Results

The measurement curves for CGS, CGD, CGC, CGB, CGG and simulation curves for all nine intrinsic caps are presented below. The CGS, CGD, CGC, CGB and CGG can be simulated and optimized using SPICE. The "Sim Only" selection provides the simulation of 9 intrinsic caps of: CBDB, CBGB, CBSB, CDDB, CDGB, CDSB, CGDB,CGGB and CGSB.


Figure 5. CGS data


Figure 6. CGD data


Figure 7. CGC data.


Figure 8. CGB data


Figure 9. CGG data.


Figure 10. "Sim. Only" data. Simulation results of:

Parameter Extraction

The CGS, CGD, CGC and CGG measurements have the capability of extracting the BSIM3v3 capacitance parameters. For parameter extraction press the "Fit" button from the "Options" menu. For example from the CGD measured data, parameters CGSO, CGDL and CKAPPA can be extracted and displayed in the graphics screen (Figure 11). The extracted parameters are also copied into the parameters screen.


Figure 11. CGD measured data and extracted
parameters CGDO, CGDL and CKAPPA.



The CGG measured data can be used to extract oxide thickness (TOX). After the measurement is completed, press the "Fit" button and the extracted value of TOX will be displayed on the graphics screen (Figure 12.)


Figure 12. CGG measured data
and extracted parameter TOX.



Simulation and Optimization

The "INT.CAP" routine allows UTMOST users to simulate and optimize the BSIM3v3 capacitance parameters with SmartSpice. The optimization of the model with SPICE using the measured data will improve the accuracy of the capacitance model. The improvement on the AC model will translate into better fits for the ring oscillator circuit simulations.

In the following example the CGC (channel capacitance) was measured when Drain and Source terminals were shorted and the Substrate was connected to DC ground. The parameters CGDO, CGSO, CGDL, CGSL and CKAPPA were optimized in the "accumulation region" and parameters CLC, CLE and DLC were optimized in the "inversion region" (Figure 13.)


Figure 13. PMOS device CGC measured and optimized simulation
results. The optimization box includes the accumulation region.




The addition of the "INT.CAP" routine enables UTMOST users to measure any combination of MOS capacitances. An independent bias from a DC analyzer can also be applied to the MOS device while the CV measurements are performed. The "INT.CAP" routine utilizes SmartSpice for capacitance simulations. Using SPICE in capacitance simulation and optimization will enhance the accuracy of the AC modeling with BSIM3v3.