Hints, Tips and Solution - November 1997


Q: How is the coupling ratio between the floating gate and control gate of a Flash EEPROM modeled in ATLAS?

A: In EEPROM devices the floating gate is capacitively coupled to the control gate and the substrate. The exact ratio of the coupling is determined by the relative shape of the floating and control gate electrodes as well as the inter-gate layer thicknesses. For most structures full 3D simulations would be required to model the control and floating gate geometries correctly. Although ATLAS/ Device3D can perform simulations of 3D Flash memory structures it is often more convienient to find a solution using 2D simulation.

By default, in 2D simulations the coupling capacitances between the floating gate and the control gate and other electrodes is determined only by the layer thicknesses and other 2D geometries. However ATLAS enables the user to specify an extra capacitance between a floating electrode and any other electrode in the device structure. Most commonly this is an extra capacitance between the floating gate and the control gate. This would be defined using the syntax:


Users should note this capacitance is applied between electrode nodes. This differs from the usual lumped capacitance definition on the CONTACT statement which applies between the specified electrode and ground.

The effect of the extra capacitance is to give the correct coupling ratio seen in simple EEPROM simulations such as the threshold voltage evalution shown in Figure 1. Generally the value of the external capacitor should be tuned to the threshold behavior before more complex simulations of programming, erasing or breakdown are done.


Figure 1. Correct setting of the coupling ratio is required
for accurate EEPROM threshold simulation.

Capacitive coupling between the floating gate and other electrodes can also be modeled by additional syntax. The syntax ELx.CAP and FGx.CAP, where x=1 to 4, can be used to define up to four different electrode names and capacitors.


Q: How can EEPROM devices be simulated in a circuit environment using ATLAS/MixedMode?

A: Any type of EEPROM or non-volatile memory from ATLAS can be embedded in a SPICE circuit and simulated using MixedMode. The ATLAS device should be defined in the circuit netlist using syntax such as:


Note that the floating gate is assigned a negative node number. This allows ATLAS to store the change on the floating gate during MixedMode simulations.

In the numerical device parameter definition of the MixedMode input file the floating gate should still be defined as a floating electrode using the CONTACT statement. The coupling capacitances described above should also be defined using the CONTACT statement and the syntax refered to in the previous question. Users should not make any connection to the floating gate node in the SPICE circuit. This especially includes capacitors between the floating gate and any node. This is due to the difference in definition of a floating node in SPICE and a floating gate in ATLAS.

Programming and Erasing simulations in a circuit environment can be performed using ATLAS/ MixedMode. Figure 2 shows a Flash programming simulation where the EEPROM device is in series with a MOS transistor simulated in SPICE. To highlight MixedMode usage the comparison shows the effect of variations in the series MOSFET on the programming curve.

Figure 2. EEPROM programming simulated in MixedMode.
Variation in parameters of the series MOSFET is used
to illustrate the effect of circuit variation.


Q: How can ‘one-shot’ EEPROM programming be modeled with ATLAS?

A: ATLAS can model the one-shot programming by mirroring the test conditions used in measurements. In this test the control gate of Flash memory device is held at a high voltage. Then the drain is ramped up from zero to a voltage around breakdown.

During the VDS ramp, at around 2-3V hot electron gate current programs the floating gate causing a VT shift. This causes the drain current to drop and hot electron current to fall off.

If a DC solution was used in ATLAS the results would be incorrect since the connection between injected gate current and floating gate charge is only possible if the time scale is known. Thus transient simulation should be used in ATLAS. The length of the transient needs to be matched to the ‘one-shot’ programming measurement setup.

However since the timescale of the drain voltage ramp is typically slow the device is in equilibrium at each time step. ATLAS includes a special numerical technique to deal with this situation defined by:


This quasistatic method adjusts the error control within ATLAS to avoid excessively short timesteps. It is relevant for all other types of quasistatic transient simulations.

Although the simulation is run as a transient mode the final results are displayed as an ID/VDS curve (Figure 3). The curve clearly shows the on-set of programming and the final punchthough.


Figure 3. ‘One-shot’ programming characteristic
of a Flash Memory device is simulated by using
quasi-static transient simulation in ATLAS.