ATLAS Simulation of SiC Devices Using Anisotropic Mobility Models

There has recently been a great deal of interest and research into using wide band gap materials, such as silicon carbide, in high power, high temperature applications. The operation of these devices has been found to be significantly different from the similar devices made using silicon. These differences are not fully explained by changing the material properties to those of SiC. Recent work has shown that the Hall mobilities in SiC are different depending on the crystalline axis where conduction is taking place [1]. This"anisotropic" mobility could dramatically affect device simulation results, particularly in power devices where current flow may be fully two-dimensional.

ATLAS has been modified so that this anisotropic mobility behavior may be modeled accurately as part of the device simulation. All of the existing mobility models implemented in ATLAS support this feature and only require the user to specify the mobility parameters in the two crystallographic planes used within the simulation. ATLAS then automatically accounts for the change in mobility as the vector of current flow moves through 360 degrees.

To illustrate the effects that this model has on numerical simulation we have performed simulations on two 6H-SiC transistor structures - the trench gated MOS (UMOS) and the double implanted MOS (DIMOS) transistor[2] - with the standard physical material parameters suggested in [3]. The mobilities were defined for the planes <0001> and <1100> which resulted in a perpendicular to parallel mobility ratio of 5 as suggested by [4]. The plane <1100> contains the greater mobility values for both electrons and holes.

Simulation Results
Figure 1 shows the first structure to be simulated, the UMOS device. The Id-Vd characteristics of this device were simulated with both the standard isotropic and the anisotropic mobility models. The results of these simulations are shown in Figure 2. Two simulations were performed using the standard mobility model - firstly with the mobility coefficients for the plane <0001> and secondly with the mobility coefficients for the plane <1100>. As shown in the results the anisotropic mobility model has given a similar characteristic to the isotropic model with mobility parameters of the <0001> plane. This result can be understood intuitively from Figure 1 as the current path is almost entirely in the <0001> plane. Also, the MOS channel, to the left of the gate, itself lies in the <0001> plane. The only current flow along <1100> will be in the n+ source region where there is only minimal resistance. As a result the mobility changes little along the current flow path and can be simulated using an isotropic mobility model.


Figure 1. Structure of the trench-gated MOS
device (UMOS) for simulation in ATLAS.


Figure 2. Simulation results of the Id-Vd characteristics of the
UMOS device using isotropic and anisotropic mobility models.
The anisotropic mobility results can be matched with one set of
appropriate isotropic mobility coefficients.

Figure 3 shows the second device under analysis, the DIMOS device. The Id-Vd characteristics of this device were once again obtained with both the standard isotropic and the anisotropic mobility models, and are shown in Figure 4. In this device three different curves are obtained.The two curves obtained from the isotropic mobility model, for planes <0001> and <1100>, are both different to that obtained using the anisotropic mobility model. This difference is a result of the current flowing partly in the <0001> plane and partly in the <1100> plane. The MOS channel lies in the plane <1100>, which is the high mobility plane,whilst the majority of the distance over which the current flows is in the <0001> plane. Therefore the on-resistance, which is controlled by the <0001> plane, will be quite high. However current saturation is controlled by the pinch-off region in the channel which lies in the<1100> plane. As a result the anisotropic model gives a higher on-resistance than the <1100> mobility but the saturation current will be close to that obtained for the <1100> plane but at a much higher drain voltage. The anisotropic model also results in a slightly different current flow path for the DIMOS device.


Figure 3. Structure of the double implanted
MOS (DIMOS) device for simulation in ATLAS.


Figure 4. Simulation results showing the Id-Vd characteristics
of the DIMOS device using both isotropic and anisotropic
mobility models. The anisotropic results cannot be matched with
just one set of isotropic mobility coefficients.

Figures 5 and 6 show the simulated current flowlines for the isotropic and anisotropic mobility models. The anisotropic model is shown to have a different current flow path. Firstly the current spreads out more in the n- region but is more dense around the corner of the p- region. This will affect both the series resistance and the self heating in the device.


Figure 5. Two-dimensional plot of the current flowlines in
the DIMOS device simulated with the isotropic mobility model.


Figure 6. Two-dimensional plot of the current flowlines in the
DIMOS device simulated with the anisotropic mobility model.
The current spreading and current concentration with this model
are different to those found with the isotropic mobility model.

A new implementation of the mobility model into the semiconductor equations allows either isotropic or anisotropic mobility behavior tobe modeled. The implementation fully supports all the mobility models that are currently included in ATLAS. Two examples have been demonstrated. For a UMOS device the anisotopic mobility model was shown to correctly match the isotropic model. In the second example, the DIMOS device, the complex two-dimensional current flow pattern can not be accurately modeled with the isotropic mobility model and only ananisotropic mobility model will yield the correct I-V characteristics.


[1] M.Schadt and G.Pensl,
"Anisotropy of the electron Hall mobility in 4H, 6H and 15R silicon carbide",
Appl. Phys. Lett., Vol.65, 1994, pp.3120-3122.

[2] B. Jayant Baliga,
"Trends in power semiconductor devices",
IEEETrans. Elect. Dev., Vol.43, No.10, 1996, pp. 1717-1731.

[3] M.Ruff, H. Mitlehner and R.Helbig,
"SiC Devices: Physics andNumerical Simulation",
IEEE Trans. Elect. Dev., Vol.41, No.6, 1994, pp.1040-1054.

[4] W.J.Schaffer, G.H.Negley, K.G.Irvine and J.W.Palmour,
"Conductivityanisotropy in epitaxial 6H and 4H SiC",
Mat. Res. Soc. Sym., Vol.339,1994, pp. 595-600.