Diagnose Process Variations By Using SPC Charts and a Wafer Map


Timely delivery of high quality products at a low cost to the market is the key to the success of VLSI business. Quality control charts have been proven to be very useful in monitoring the quality of the products and assisting in finding the possible causes of process deviations from normal values. In this article we demonstrate how to use the combination of statistical process control charts (SPC) and a wafer map display in order to assist process and integration engineers identify possible process steps that cause low yield.

Figure 1. Statistical process control chart for leakage current as a function of wafer number.

SPC Chart to Identify Out of Control Points

In this article we are going to utilize a data set that consists of leakage measurement data to demonstrate how to identify out-of-control datapoints. After loading a dataset into SPAYN, an attribute search is performed to get the 999 sets of data collected from Lot1. Nine wafers from this particular lot were measured. From the Charts menu, invoke the SPC chart. The statistical data of the controlled measurement is used to define the control limits. All available data should be used to determine the control limits. If the process is in statistical control, the control chart will show random oscillations without any definable pattern. A point outside the control limits, or some visible trend such as a sequence of points on one side of the center line signals that the process is going out of control. In Figure 1, we see that the average value from Wafer six is outside the limits. The control charts only signal a problem, they do not in any way reveal the cause. To find the cause of process problems, we need to use the wafer map display of the parameter in order to obtain more information.

Figure 2. Wafer attributes selection table.


Spatial Distribution On A Wafer

Perform Data Search->Search Results->Wafer Map... operations to invoke the wafer map. If the data file was originally generated using Utmost, then the die location information is already available in the die name. Load the die location as Utmost which means no additional die location file is needed. SPAYN will read the die location information from the die name. By using the SetUp feature on the wafer map window select the particular wafer for analysis. Lets select wafer six. Then display the Id_leak values on the wafer map (Figure 3). This display gives the spatial distribution of Id_leak values on a wafer map. By using different colors to represent different ranges of values, an indication of the cause of low yield is obtained. In this display of Id_leak, one could easily see that high values of leakage current are distributed towards the boundary, especially the right side of ring of the wafer which is a strong indication that there are some problems with some of the process steps. So we could draw the conclusion that something must be modified on the etching, thermal cycle, or implanter setup which could possibly contributed to such a pattern.

Figure 3. Wafer Map display showing distribution of leakage current.