AC Model Validation Using Transient Analysis

Part 2


In a previous issue of the Simulation Standard, September 1996, DC model validation procedure using UTMOST was introduced.

DC model validations are very important but AC model validations, typically using time domain analysis of the propagation delay of ring oscillators, or rise/fall times of inverters, or other suitable circuits are crucially important to perform.

Measurement and parameter extraction of devices capacitances is difficult and not very accurate due to their small values and complex inter-relationships. Even though specially designed capacitance test structures are used for measuring and extracting these capacitance parameters, most of the fringing parasitic effects are neglected and extraction accuracy is poor. Among all capacitances, area and sidewall capacitances are extracted with a reasonable accuracy, and oxide overlap capacitances are extracted with very poor accuracy.

Once all capacitances are extracted and a final model is put together, it is necessary to verify the entire model accuracy in the transient operation. Additional inaccuracies may come also from a complex inter-relationships that exist between the DC and AC models.

These relationships are typically neglected during the DC and AC model parameter extraction.

AC Validation Solution

To properly validate the entire SPICE model the user should design a ring oscillator with a varying number of stages. Typically 21 to 101 stages are recommended depending on the technology (TFT versus CMOS) and desired accuracy. The measurement of the ring oscillator delay is preformed with a sampling scope (UTMOST supports a large number of HP and Tektronix scopes) at a constant DC bias. If the DC bias is stepped a number of curves displaying delay versus DC bias can be obtained (Figure 1).

Simulation of these delay curves reveals the initial quality of the entire SPICE model for the first time. Depending on how inaccurate is the initial model, the user can select an arbitrary number of DC and AC parameters to optimize. Typical parameters to optimize are CGSO, CGDO for AC, and LD, WD for DC.

The optimization procedure must be performed through the VYPER interface using as target SPICE a circuit simulator used by circuit designers at a customer site. This way, the model accuracy is guaranteed for the SPICE simulator used at a local customer's site.


Figure 1. Typical measured data of a propagation delay of a ring oscillator versus bias.

Figure 2. Select a file describing a netlist of a ring oscillator, control card for transient analysis, and an initial model.

UTMOST Operation

In order to simulate and optimize the ring oscillator circuit, macro-modeling facility of UTMOST should be utilized. The proper netlist, control card and the model file should be generated for the "timering" routine in the UTMOST TFT technology. Follow the below provided steps to optimize the delay for a ring oscillator circuit:

Press the SPICE button in the main VYPER window and select the "open" option from the menu. This will open the "Run SPICE" screen.

Enter a netlist name in the text field across from the title "Netlist" and press the left arrow key to open a netlist file.

Figure 3. A typical netlist of a ring oscillator

Enter a proper ring oscillator netlist as described in Figure 3 and press the"store" button to save the file.

Figure 4. Typical control file for transient analysis of a ring oscillator.

Repeat the last two steps for the control card based on the example given in Figure 4.

For the Library (model) file, create a model file for the N and P type devices in your vyper_data/model directory. Comply with the library format presented in Figure 5. After the model file is created press the left arrow button across from the library and select the "include library"option. Enter the model file name which is created under the vyper_data/model directory and press the add button.

Figure 5. A typical initial model set for n and p type TFT devices.

At this point the combination of the netlist, control card and a library file should be a proper ring oscillator input deck for simulation in SPICE.

Enter the control file name in the main VYPER screen.

Press the VYPER Files button and select the control file store option.This will open the "Create Task" screen.

Enter the correct UTMOST Routine number. This number should be 31 for the timering routine in TFT technology. Press the Apply button to create the control file.

Press the "To vyper" button in the main UTMOST screen. The new control filename should appear in the "Multi Target Routine Control" screen. Press the select button and then the "Send Control File" button. The "SPICE Table completed" message should appear in the main UTMOST screen. This step will create a proper model table in the UTMOST parameter screen for each device containing a SPICE model.The model sets for different elements can be viewed by toggling the "Model Number"button in the parameters screen. (Figure 6).After selecting proper parameters for each element, global optimization can be started for the ring oscillator circuit (Figure 7).

Figure 6. Parameter screen initialized from the initial model set described in Figure 5.

Figure 7. Typical example of a global optimization of device parameters to improve ring oscillator delay simulation accuracy.