Modeling MOS Devices Using the MASTAR Model with UTMOST III

Christian Denat , France Telecom CNET, BP 98, 38243 Meylan Cedex, France
Email : Gilles Gouget, SILVACO Data Systems SARL, 8, Av. de Vignate, 38610 Gieres, France Email :


The MASTAR model [1] is now available to UTMOST III users. This model was developed by France Telecom CNET in one of its laboratories near Grenoble in France.

After a significant amount of testing and verification, a first version of the MASTAR extraction algorithm has been formulated [2]. As CNET was one of the first European users of UTMOST III, work on an UTMOST III implementation of the MASTAR model and extraction procedure began in 1993. As a result of the feedback of internal designers who have used MASTAR since 1994, both the MASTAR model and the extraction methodology are now very accurate and flexible.

The result of these two years of improvement was MASTAR v2.0 [3] which was fully integrated into an in-house version of UTMOST III and used on several technologies, from 1µm down to 0.25µm and 0.18µm R & D processes, over a large range of temperature
(up to 125 °C).

The close working relationship between CNET and Silvaco has resulted in a complete integration of MASTAR v2.0 into UTMOST III. This article presents the three new extraction routines which have been added to UTMOST III. Some results are also shown. These routines introduce some new concepts in UTMOST III which will be explained here.

Overview of The Extraction Routines

Three new routines have been added to UTMOST III. These are the LO_MAST, VT_MAST and SUB_MAST routines.

The first routine, LO_MAST, is dedicated to the extraction of sheet resistance, mobility parameters, and channel width and length reduction parameters.

The second routine, VT_MAST, is used to extract all of the threshold voltage model parameters, and the SUB_MAST routine is used for the extraction of subthreshold parameters.

The best strategy to extract MASTAR parameters is to use LO_MAST first, followed by VT_MAST and then SUB_MAST. Thus, by the time VT_MAST and SUB_MAST are executed good estimates of the source and drain resistance parameters and the geometry reduction parameters are known. Also it is important that good threshold voltage parameters have been extracted by the VT_MAST routine before the SUB_MAST routine is activated.

All other MASTAR parameters are obtained using UTMOST III local or global optimization procedures.

The philosophy used during the implementation of the MASTAR extraction routines was to create very simple, flexible, and robust methodologies.

Automatic device sorting

From the device set selected by the user, the three MASTAR routines are able to automatically sort the devices by width and length. For the VT_MAST and SUB_MAST extraction routines, some parameters must be extracted from a large device. These two extraction routines will firstly find the large device and then sort the remaining devices in accordance with their needs.

Default values

One of the main problems of parameter extraction, particularly for a process under development, is to achieve realistic and physical results. The three MASTAR routines use the values defined in the minimum and maximum columns of the UTMOST III Parameter Screen to check each of the extracted parameters. In cases where an extracted parameter value is outside of these limits, the parameter is forced to the value defined in the user column of the UTMOST III Parameter Screen.

Model Mobility, Resistance, and Geometrical Reductions Parameters

The LO_MAST routine collects IDS-VGS measurements on W and L arrays at low values of drain bias without any bulk effect (i.e. with VBS = 0V). The extraction methods and concepts are based on those explained in [3]. In Figure 1 it can be seen that the temporary parameter M0 (mu0.Cox.W/L) is at the heart of this extraction.

Figure 1. Extraction of MASTAR DL, DW, Sheet resistance and mobility parameters.

On all of the L-array devices, a preliminary extraction is done to extract the total ohmic resistance RT (Rs+Rd). In a second iteration RT is taken into account and all devices are analyzed. In the top right portion of Figure 1, plots of TG (gate mobility modulation) versus M0 for the L-array devices can be seen where the slanted line is the first iteration without the effect of RT. It is easy to demonstrate that the slope of this line is RT, and that the intersection with the Y axis is TG.

A simple way of checking the accuracy of this extraction is to take into account the extracted RT and make the extraction a second time. We then obtain the horizontal curve Y=TG and now RT=0.

The two other plots represent the extraction of DL and DW by plotting 1/M0 versus L and M0 versus W respectively. DL and DW are then obtained using the intersection of the fitted linear regression model with the L or W axis.

Threshold Voltage Parameter Extraction

This portion of the model was the most critical during the formulation of both the model equations and the extraction method.

Two new concepts were introduced into UTMOST III. One concerns threshold voltage (VTH) measurements, and the other concerns parameter optimization.

VTH Measurement

Previously each MASTAR DC routine measured, utilized and saved IDS versus VDS, VGS, and VBS curves. In order to extract the VTH model parameters, there was a requirement to perform IDS-VGS measurements over a large range of VBS and VDS biases. It is easy to understand that this is very inefficient in terms of measurement time and media storage. Moreover, another problem was the choice of an accurate methodology to extract VTH at high VDS biases.

Therefore, we chose to develop a new method for the VTH extraction, which is applicable over the entire range of drain biases. Thus, this routine works on a VTH measurement concept instead of the classical method of performing VTH extractions on IDS-VGS measurements.

At VGS = VTH, the threshold current can be expressed as

ITH = Constant W/L*(bias dependences) [3]

For a large device we could measure Ith_large with a classical method, at VBS=0 and a small value of VDS.

We then calculate a normalized current

Inorm = Ith_large.L/W/(bias dependences) = Constant

Thus, for all devices, irrespective of the VDS and VBS voltages, the drain current at VGS = VTH is

ITH = Inorm*W/L*(bias dependences)

All of the data is known so we can do a reverse calculation of the VGS needed to obtain the value of ITH. For any device at any bias, except for the largest device at VBS = 0 and a low VDS, a new bisection VTH measurement method is used. The VGS start and stop values, often used as start and stop points for the VGS sweep are used in VT_MAST as the initial lower and upper bounds of the bisection. VTH is obtained when the relative error on ITH is less than 2% or when the working interval in VGS is less than 10 mv wide.

This method is very attractive and efficient in terms of accuracy (+/- 5 mv), speed (about 10 measurement points required whereas a classical method needs three or four times more measurements), and in terms of data storage (less than 20 data points per device required instead of up to 1000 for other methodologies).

VTH optimization

As the extraction is relatively complex, and needs a complete set of VTH versus L, W, VDS or VBS data, it is sometimes necessary to correct or tune some parameter values resulting from the direct extraction.

For this reason the VT_MAST routine is able to perform parameter optimization on VTH measurements versus VDS at 2 values of VBS (0 and and highest one) for all of the measured devices (see Figure 2). This possibility is completely new in UTMOST III and allows the user to fit the threshold voltages to within an accuracy of 2% (RMS).

Figure 2. Optimization of VTH with VTH_MAST.



Figure 3 shows a complete comparison between VTH measurements and the MASTAR VTH model simulations. It can be seen on the VTH vs L plot that the roll-up and short channels effects are well modeled.

Figure 3. Comparisons between measured and modeled VTH values.

Subthreshold Current

All of the MASTAR parameters influencing the subthreshold region are obtained using the SUB_MAST routine. Selected devices are the large device and all of the L-array devices. The measurements required are IDS-VGS sweeps for two VBS and two VDS values. Particular attention is paid to having a very accurate extraction of the subthreshold slope.

Optimization Stage and Results

All of the remaining MASTAR parameters are obtained using the ALL_DC routines. Generally, the subthreshold and linear region parameters are not in need of further refinement. Global or local optimization procedures can be applied to the IDS-VDS and RDS-VDS characteristics in order to obtain very accurate NMOS and PMOS results in the regions of operation (ohmic, saturation, and avalanche) existing in these plots. This accuracy is shown in Figures 4 through 7.

Figure 4. Log(IDS) versus VGS plots for NMOS devices (T=27 C, VDS = 100mV, VBS= 0, -1.650, and -3.3 Volts) [ Measured (____) and MASTAR (+++++) ].

Figure 5. Log(IDS) versus VGS plots for PMOS devices (T=27 C, VDS = -100mV, VBS= 0, 1.650, and 3.3 Volts) [ Measured (____) and MASTAR (+++++) ].

Figure 6. IDS-VDS and log(GDS)-VDS plots for NMOS devices (T=27 C, VBS = 0, VGS = 1.1, 2.2, and 3.3 Volts) [ Measured (____) and MASTAR (+++++) ].

Figure 7. IDS-VDS and log(GDS)-VDS plots for PMOS devices (T=27 C, VBS = 0, VGS = -1.1, -2.2, and -3.3 Volts) [ Measured (____) and MASTAR (+++++) ].


This article has given an introduction to the three new UTMOST III routines dedicated to the extraction of MASTAR model parameters. It has been shown that the MASTAR MOSFET model, predicts measured device characteristics (currents and conductances) very accurately. The MASTAR model has been implemented in the ELDOTM circuit simulator and it is used for analog as well as for digital applications.

The data used in this article is from a 0.35µm CMOS process developed in the France Telecom CNET and SGS Thomson Common Center R & D facilities in Crolles (France).


The authors would like to acknowledge Dr. Ivan Pesic and Dr. Seamus Power of SILVACO HQ for their help and advice during the integration of the MASTAR model and extraction algorithms into UTMOST III, and Thomas Skotnicki and Gerard Merckel of France Telecom CNET who designed and developed the MASTAR model and part of the extraction algorithms.


1] T. Skotnicki, C. Denat, P. Senn, G. Merckel and B. Hennion, "A New Analog/Digital Model for Sub-halfmicron MOSFETs" , 1994, IEDM,
San Francisco (CA), USA

2] M. L. Rostoll, "Mise au point des procedures et validation d'un model CAO ...", Rapport de Stage de DESS Composants Electroniques, Universite de Rennes
I, Apr-Jun 1992

3] C. Denat, T. Skotnicki and G. Merckel, "Mastar version 2.0 Model and Parameter Extractions", France Telecom CNET, Note Technique NT/CNS/DCF/74,
July 95