Parameter Extraction for the EKV MOSFET Model with UTMOST III

M. Bucher, C.C. Enz , C. Lallement and F. Krummenacher, Swiss Federal Institute of Technology (EPFL), Electronics Laboratory, ELB-Ecublens,CH-1015, Lausanne, Switzerland G. Gouget, M. Taner, and J.A. Power, Silvaco International


An analog circuit simulation MOSFET model should fulfill a list of requirements, the most important of which are validity in all regions of device operation and continuous transitions between them. The model should describe the essential physical behavior of the MOS device with varying currents, voltages, geometries, temperature and noise, and provide the user with adequate information on the operation mode of the device. The model should be adequately parameterized, and the number of parameters kept reasonably low to allow for better physical insight and to ensure the model's performance.

The Enz-Krummenacher-Vittoz (EKV) model, described in references [1][2][3][4], has recently found a larger availability as a public-domain model, and a growing community of designers is using it in academic as well as industrial environments, on a variety of platforms, circuit simulators and parameter extraction tools including UTMOST III.

An article in the May 1995 issue of the Simulation Standard introduced version 2.2 of the EKV model and assessed its potential. Version 2.3 of this model is now available in UTMOST III and will be described in a future issue of the Simulation Standard. This article will describe the dedicated EKV extraction routine which has been implemented into UTMOST III in collaboration with the EPFL in Switzerland.

EKV Model Background

The symmetry of the transistor can be preserved by referring all voltages to the local substrate. The state of any point of the channel of a transistor is controlled by VP-Vch, where the non-equilibrium voltage Vch simply called channel "potential" is produced by drain and source voltages VD and VS, and VP is the pinch-off voltage depending only on the gate voltage VG. This state can be characterized by the degree of inversion of the channel. Weak inversion for VP < Vch corresponds to a density of mobile charge that can be neglected in the field calculations, whereas strong inversion for VP > Vch corresponds to a large density of mobile charge which clamps the surface potential to a value that can be approximated as constant. The various possible modes of operation (conduction, forward and reverse saturation, weak inversion, and blocked) depend on the degree of inversion at each end of the channel, and therefore on VP - VS and VP - VD.

Using the charge sheet model with the assumption of constant doping in the channel, the drain current ID can be expressed as the difference of a forward component IF and a reverse component IR. Each of these is proportional to a function of VP - VS respectively VP - VD where the specific current IS is the proportionality factor. This function is exponential in weak inversion and quadratic in strong inversion. It can be continuously interpolated in between. A description of ID(VG, VS, VD) from weak to strong inversion for the long-channel transistor requires a total of only four parameters: the mobility related parameter KP, the threshold voltage VTO, the substrate effect parameter GAMMA and the surface potential in strong inversion at equilibrium PHI. Second order effects such as mobility reduction due to the vertical field, velocity saturation, channel length modulation and short-and-narrow-channel effects are then taken into account with the addition of additional parameters.

The EKV model is based on the above reasoning and contains the following DC room temperature parameters which require extraction:


Parameter Description Units
VTO Zero bias threshold voltage V
GAMMA Body effect parameter V0.5
PHI Bulk Fermi potential V
KP Transconductance parameter A/V2
THETA Mobility reduction coefficient V-1
UCRIT Longitudinal critical field V/m
LAMBDA Depletion length coefficient -
DL Channel length correction m
DW Channel width correction m
LETA Short channel effect coefficient -
WETA Narrow channel effect coefficient -
IBA First impact ionization parameter m-1
IBB Second impact ionization parameter Vm-1
IBN Third impact ionization parameter -
RS Extrinsic source resistance ohm
RD Extrinsic drain resistance ohm
RSH Extrinsic sheet resistance ohm/square
RSC Source contact resistance ohm
RDC Drain contact resistance ohm

Parameter Extraction

The UTMOST III EKV extraction routine is closely based on the methodology developed at the EPFL [4, 5]. The full extraction sequence is composed of three parts, with the first part being optional.

In part 1 the routine will measure linear region IDS-VGS curves (VBS = 0V) for a long, a short, and a narrow device.Values for the KP, DL, and DW parameters are extracted. These values are meant to provide useful initial parameter estimates for subsequent ALL_DC local optimization procedures for the EKV model. Figure 1 shows some typical measured data for NMOS devices with drawn geometries of 20/20, 20/1, and3/20 µms.

Figure 1. Typical measured EKV IDS-VGS characteristics for NMOS devices.

In part 2 of the EKV extraction process sqrt (ID) versus VS measurements are measured for the three chosen devices. The object of this extraction stage is the determination of the device specific currents (IS) since knowledge of these currents is required for the next extraction stage. The specific current can be easily extracted in strong inversion and saturation from the sqrt (ID) versus VS characteristics. The specific current is twice ID when VS is equal to VP. Typical measured sqrt (ID) versus VS characteristics, along with the extracted IS values, are shown in Figure 2.

Figure 2. Typical measured EKV sqrt (ID)-VS characteristics for NMOS devices for specific current extraction.

In the final stage of the EKV extraction routine the device is biased according to the circuit schematic shown in Figure 3. For HP4145 and HP4142 DC Analyzers UTMOST III will perform the measurements on this circuit automatically and without any user intervention. Then VP versus VG characteristics are measured by setting the drain current equal to half the specific current (IS) in saturation, sweeping the gate voltage, and measuring the source voltage which is a reflection of the pinch-off voltage (VP).

Figure 3. Circuit for VP versus VG characteristic measurements.

The VTO, GAMMA, and PHI parameters are extracted from the VP versus VG characteristics measured from the large device. VTO is determined as the value of VG which VP=0. Estimates for the LETA and WETA parameters are then extracted from the VP versus VG characteristics measured from the short and narrow devices respectively. During the extraction of VTO, GAMMA, PHi, LETA and WETA from the pinch-off voltage characteristics use is made of an analytical expression for the pinch-off voltage. The entire model equation set is not evaluated. Figure 4 shows plots of measured and fitted VP versus VG characteristics for the three devices under analysis here. By enabling the VTO, GAMMA, PHI, LETA, and WETA parameters for optimization in the UTMOST III Parameters window and performing an optimization the results can be improved further as can be seen in Figure 5.

Figure 4. Plots of measured (++++++) and fitted (-----------) VP versus VG characteristics for NMOS devices.

Figure 5. Plots of measured (++++++) and optimized (----------) VP versus VG characteristics for NMOS devices.

The remaining EKV parameters can be easily and accurately determined using UTMOST III local optimization strategies. These will be discussed in a future Simulation Standard article.


The EPFL-EKV MOS model is presently available in several circuit simulators. This model has only ten physical parameters (COX, VTO, GAMMA, PHI, KP, THETA, UCRIT, DW, DL, XJ), three fine tuning fitting coefficients (LAMBDA, WETA, LETA), three parameters for impact ionization current (IBA, IBB, IBN), four additional temperature parameters, and two 1/f noise parameters (KF, AF). UTMOST III currently supports the latest EKV equations.

A complete parameter extraction methodology has been formulated specifically for this model. In particular, the parameter extraction from the measured pinch off-voltage characteristic at constant current is of importance. This methodology has been implemented into UTMOST III and was described in this article. Experimental data validate the static model and the associated parameter extraction and show their applicability over a wide range of CMOS bulk and fully depleted SOI processes [5].

The EKV model features the most important properties for a MOS simulation model such as accuracy and continuity within all operation regions making it suitable for analog design. Work is underway to improve the modeling of short channel effects and the scalability of the model. address short-channel effects and scaling behavior. It is hoped that this will extend the model's applicability to deep submicron technologies. With the recent availability of this model, an increasing number of circuit designers are using the EPFL-EKV model.


[1] C. C. Enz, F. Krummenacher and E. A. Vittoz, "An Analytical MOS Transistor Model Valid in All Regions of Operation and Dedicated to Low-Voltage and Low-Current Applications," special issue of the Analog Integrated Circuits and Signal Processing journal on Low-Voltage and Low-Power Design, vol. 8, pp. 83-114, July 1995.

[2] C. C. Enz, "The EKV Model: a MOST Model Dedicated to Low-Current and Low-Voltage Analog Circuit Design and Simulation", Chapter 7, Low-Power HF Microelectronics, Ed. G. A. S. Machado, IEE Circuits & Systems Series no. 8, to be published 1996.

[3] C. C. Enz and E. A. Vittoz, "Low-Power Analog CMOS Design", Tutorial of the ISCAS'96, to be published by IEEE press as a chapter of "Emerging Technologies", 1996.

[4] G. Machado, C. C. Enz and M. Bucher, "Estimating key parameters in the EKV MOST model for analogue design and simulation", Proc. IEEE ISCAS'95, April 29-May 3, 1995.

[5] M. Baucher, C. Lallement and C.Enz, "An efficient parameter extraction methodology for the EKV MOST Model" Proc. IEEE Int. conf. on Microelectronic Test Structures (ICMTS), Trent, Italy, March 25-28, 1996.