Q: How can I remesh my process simulation result for device simulation?

A: The structure editing and griding tool DevEdit provides an effective way to remesh structures between process and device simulation.

DevEdit is able to read and write files to both ATHENA and ATLAS. In addition to the graphical user interface, DevEdit can operate in batch mode under DeckBuild. The batch mode DevEdit features a powerful syntax that can be applied to remesh structures read directly from ATHENA. DevEdit employs a heirachical method for remeshing existing structures. Users specify mesh parameters at each stage. Initially a base mesh is applied with the command:


This mesh of h1 by w1 microns provides the coarsest mesh in the structure. On top of this base level mesh DevEdit determines which points must be added to ensure the geometry of all regions is preserved. Optional boundary conditioning to smooth region boundaries can be applied using the BOUND.COND statement.

Mesh constraints can be applied to arbitrary boxes with the device using the syntax:

constr.mesh x1=<n> x2=<n> y1=<n> y2=<n>\
max.height=<h2> max.width=<w2>

This sets the maximum mesh size to h2 by w2 microns the box with diagonal from (x1,y1) to (x2,y2). Using the constraint boxes in critical areas of the device is the most effective way to use DevEdit. In MOSFETS the constraint boxes can be applied to the silicon region under the gate. Typically vertical grid spacings of 5 are required for accurate simulation of channel conduction in sub-micron MOSFETs.

Use of multiple constraint boxes can be applied. For MOSFET breakdown constraint boxes can be applied to the drain/gate overlap area.

In addition to constraint boxes, DevEdit can refine on quantities such as individual doping species, net doping, potential. The IMP.REFINE statement allows users to select the critical value of a quantity for refinement and an associated minimum grid spacing. This type of refinement is useful when key effects are located very close to junctions. For example the emitter-base junction in bipolar transistors.

The final level of grid refinement are "manual refine boxes" defined using:

Refine Mode={Both|x|y} P1=x1,y1 P2=x2,y2

These are boxes with a diagonal from (x1,y1) to (x2,y2) inside which the grid spacing is halved in the given direction. These can be used as a final customization to the mesh. In general however the constraint boxes described above are easier to use.

As a demonstration of the effectiveness of regriding using DevEdit Figures 1 and 2 show meshes created from the same process simulation structure. Figures 3 and 4 show the Id/Vds and breakdown characteristics respectively of the device for each mesh. The mesh at the silicon surface is identical in both cases to a depth of 100A. However the mesh below this is much coarser in Figure 2. However the device results show no significant change despite the reduction in the node count by a factor of two.


Figure 1

Figure 2

Figure 3

Figure 4
Demonstration of optimized griding using constraint boxes in DevEdit. Both very fine and optimized mesh produces equivalent results