Model Validation Using SmartSpice

Model validation is a very important and often neglected task. A rigorous model verification procedure should follow the extraction of any SPICE model parameter set which is destined for use by the circuit design community. This is especially true in the case of analog designs. The importance of achieving accurate and scalable predictions of device current and conductances for analog and mixed analog-digital applications is well understood. However, there may be little point in having a very accurate model if inherent discontinuities associated with the model lead to sporadic non-convergence related circuit simulation failures. This article will describe how SmartSpice can be used to efficiently execute some very useful bench-mark tests which can aid in the identification of potential model-related circuit simulation problems. The models which will be analyzed here are the BSIM3v3 and MM9 models which were extracted and reported on in the "Extraction of Scalable Temperature-Independent BSIM3 (Version 3) and Philips Level 9 MOSFET Models Using UTMOST" article which appeared in a previous issue of the Simulation Standard [1]. The accuracy and scalability of these models in terms of their prediction of device currents and conductances was discussed in [1]. In this article we will concentrate on issues such as the continuity of the predicted device currents and conductances resulting from the use of these models.


Model Validation Requirements

There are a few very good publications which list some of the requirements of a good model required for use in analog applications. The following is a listing and brief description of the model tests proposed by Tsividis and Suyama [2]:

1) The model should predict accurate I-V and C-V device characteristics.
In addition, the model should conserve charge.
2) The model should accurately predict the small-signal device conductances
and capacitances. The model must be continuous in this respect also.
3) Nonquasi-static (NQS) device behavior should be modeled.
4) Accurate noise predictions (white and 1/f) should be attainable.
5) 1-4 above should be true for all bias ranges and regions of device operation.
6) 1-4 above should be true over the entire operating temperature range.
7) 1-4 above should be true for all device geometries.
8) The model should be truly scalable i.e. only one set of parameters should
suffice for all devices of the same polarity for the process in question.
9) Warnings should be given when the model is being used outside of its
range of validity during circuit simulation.
10) The model should have as few parameters as possible and the equations
should be as physically-based as possible.
11) The composition of efficient parameter extraction strategies should
be possible for the model in question.
12) Ideally the model should provide links to device and reliability simulators.

To some extent, for the BSIM3v3 and MM9 model parameter sets in question, tests 1, 2, 5, 6, 7, 8, and 10 were addressed in [1]. Neither model is truly physical because the use of empirical fitting parameters seems to be unavoidable in the formulation of an accurate scalable sub-micron MOSFET model.

Model discontinuities associated with 1 and 2 above are often not detected simply by viewing measured versus simulated device characteristics as shown in [1]. The use of a circuit simulator is required to "zoom" into and analyze the regions of device operation where model continuity problems are likely to occur. The bench-mark test circuits proposed by the SEMATECH compact modeling group [3] were analyzed using SmartSpice. The results of some of these tests (mainly associated with tests 1 and 2 above) will be described here. In addition, information is presented which makes the execution of these tests and the analysis of the ensuing results more efficient.


SmartSpice Circuit Test Examples

The SmartSpice model bench-mark tests were configured to run in batch-mode so as to give the maximum amount of automation. The tests were also configured in such a way as to allow the simulation to be performed for both the BSIM3v3 and MM9 models. As an example the gm/IDS model test will be examined here. Figure 1 shows the SmartSpice input netlist for this test. This file also contains options, parameter definition, analysis and output statements.

The input file in Figure 1 sets up the simulation of gm/IDS curves for a 10/0.8µm NMOS device. The gate voltage is swept from 0V to 1.5V in steps of 0.01V and the gm/IDS curves are created for VBS biases of 0V and -2V. The .model statements are not contained in this file and their inclusion will be discussed below. The circuit simulation is performed using the following command


where is the file shown in Figure 1. The simulate script is given in Figure 2. The purpose of this script file is to append the file called model.card to the input file, run the simulation, and then save the results into the appropriate .out and .raw files. The model statements are separated from the main input file so that the user can easily rerun the entire set of bench-mark circuits for different models by merely changing the model.card file.


* Gm/Id Test
* The object of this test is 
to check the transconductance-to-current ratio * gm/IDS (gmids) vs VGS, including VGS values well below threshold. * gm and IDS curves can also be analyzed. **** Options .OPTION TNOM=27 GMIN=1e-14 NUMDGT=9 NOMOD BRIEF **** Parameters. .PARAM width=10u len=0.8u **** Net list. M1 1 2 3 4 nch w='width' l='len' VD 1 5 DC 0.1 VG 2 6 DC 1 VS 3 7 DC 0 VB 4 8 DC 0 VDSENSE 0 5 DC 0 VGSENSE 0 6 DC 0 VSSENSE 0 7 DC 0 VBSENSE 0 8 DC 0 **** Analysis .DC VG 0.1 1.5 0.01 sweep VB 0 -2 -2 **** Output Statements. .LET ids=i(VDSENSE) .LET gm=@M1[gm] .LET logids=log10(ids) .LET gmids=gm/ids

Figure 1. The SmartSpice input file
for the NMOS gm/IDS bench-mark test.



spice="/alpha/bin/SmartSpice -V 1.3.6.A"

if [ $# -eq 0 ] 
   echo "Usage: $0 [list of input files]"  
   exit 1

trap " [ -f $deck ] && 
\rm -f $deck; exit" 0 1 2 15 for infile in $* do file=`basename $infile .in` echo Simulating [$infile].... # Append the model cards to the net list. if [ -r $suffix ] then echo Appending
$suffix to $infile cat $infile $suffix > $deck else cp $infile $deck fi echo " "spice -b $infile
-o $file.out -r $file.raw $spice -b $deck
-o $file.out -r $file.raw echo echo Finished [$infile]...... echo \rm -f $deck done

Figure 2. The 'simulate' script used
for all of the bench-mark test circuits.


In the case of this example the simulation is performed for both BSIM3v3 and MM9 models. The model.card file referenced in the simulate script is shown in Figure 3. The model parameter library files are called bsim3v3.lib and mm9.lib. The results of the simulations are stored in .raw files which can be subsequently viewed using SmartSpice run in interactive mode.

**** BSIM3v3 and MM9 Models

.LIB '../models/bsim3v3.lib' bsim3v3


.LIB '../models/mm9.lib' mm9

Figure 3. The contents of the model.card file.


In order to simplify the user's analysis of the simulation results, it is possible to create SmartSpice scripts which will load the results from selected bench-mark simulations and automatically plot or analyze these results as desired.

The results of performing the simulation using the bench-mark example for the gm/IDS test are displayed in Figure 4. Figure 4 shows the gm/IDS versus VGS plots for the BSIM3v3 (continuous lines) and MM9 (broken lines) models. The results of performing the equivalent PMOS test are also shown.


Figure 4. Plots showing the results of
the NMOS and PMOS gm/IDS
bench-mark tests.
BSIM3v3 (____) and MM9 (____).


The gm/IDS bench-mark test showed that both models had continuous currents and transconductances under the bias conditions imposed. The BSIM3v3 curves did exhibit some anomalous behavior near threshold, especially at non-zero substrate biases. This behavior did not constitute a discontinuity but would probably lead to inaccurate transconductance predictions in the moderate inversion region of operation. The behavior in question was not visible in plots of IDS or gm when viewed individually.

Bench-mark circuits were also analyzed which looked at (a) current and output conductance predictions for gate drives close to the threshold voltage, (b) transconductance predictions for a wide range of gate voltages, and (c) IDS current predictions in the moderate inversion region. Many other bench-mark circuits were also implemented and they addressed issues such as Isat versus temperature, Isat versus substrate voltage, drain/source diode voltage versus temperature and substrate voltage, Isat versus device drawn length and width, diode voltage versus drawn length and width, and intrinsic capacitance versus terminal voltage behavior. A device symmetry test was also examined. Plots associated with tests (a), (b), and(c) above are shown in Figures 5 to 7 respectively.


Figure 5. Plots of IDS and gds versus VDS
for an NMOS device biased at VGS
voltages near to the device threshold voltage.
BSIM3v3 (____) and MM9 (____).


Figure 6. Plots of PMOS gm versus V GS.
BSIM3v3 (_____) and MM9 (____).


Figure 7. Plots of PMOS IDS versus VGS in the
moderate inversion region of operation.
BSIM3v3 (____) and MM9 (____).


No major model problems were detected for either the BSIM3v3 or MM9 model parameter sets using the bench-mark tests used. This reflected the significant improvements which these models offer over previously available commercial MOSFET models.



Model verification or model validation is an essential part of the parameter extraction process. Parameter extraction tools like UTMOST can perform many of the validation tests required but certain tests require the use of a circuit simulator. This article described how certain bench-mark circuit tests can be efficiently performed and how the associated results can be analyzed using the SmartSpice circuit simulator. Some examples of typical model validation analyses were shown but many others were also implemented and may be described in future issues of the Simulation Standard.



  1. Simulation Standard, Volume 7, Number 11, November 1995.
  2. Y.P. Tsividis and K. Suyama, "MOSFET Modeling for Analog Circuit CAD: Problems and Prospects," IEEE Journal of Solid-State Circuits, Vol. 29, No. 3, March 1994.
  3. Report of SEMATECH Compact Models Workshop, Sunnyvale, California, August 1995.