Evaluation of a Recessed Channel SOI Technology for Scaling and Optimization

There are many variables that effect the performance of thin submicron recessed- gate SOI mosfets. Among these, buried oxide layer thickness, recess depth, and active silicon layer thickness all contribute to the overall performance of the device. For the Recessed Channel SOI technology (RC SOI), process optimization is additionally complicated due to the need to optimize both the forward and back threshold voltage.

The effects of scaling the layer thickness on a Recessed Channel SOI process was evaluated. A nominal RC SOI process was used as the basis for an experiment using the Virtual Wafer Fab.

The process variables chosen for the experiment were the buried oxide layer (BOx) thickness and the active silicon layer thickness (via the recess depth). The effect the BF2 Vt adjust implant dose on threshold voltage was also included. It is important to scale the Vt adjust implant dose as the active silicon layer thickness changes. The output parameters were the forward threshold voltage, back threshold voltage and the output drive current Idsat.


The flow of this experiment proceeds as follows. First a mask was defined to provide for the etching of the channel recess. A full SOI mask set could have been used but was deemed unnecessary. Next, the nominal process flow was entered. Alternatively, a previously defined Athena command file could be used. VWF would store this as a process object for use in an experiment. A typical RC SOI device structure is shown in Figure 1.

Figure 1. Typical RC SOI Device Structure.

The next step was to create the Atlas device tests to provide the electrical characteristics. Tests for IdVg and IdVd were created. This experiment focused on the n channel device but a similar technique could be applied to the p channel. Once the experimental flow has been entered, splits may be defined.

Splits are defined through the flow editor in VWF. This allows the user to choose any command line and parameter as a split point. Even multiple split points per line are allowed (eg, implant energy, dose, and even species). VWF also allows calibration parameters to be chosen as split points for multidimensional calibration. The split points and the individual values used in this experiment are listed in Table 1. The silicon recess depth split was accomplished by using the layout interface MASKVIEWS. The design of experiments used for this experiment was a full factorial.


Parameters Split values
BOx Thick 0.12, 0.085, 0.4
Recess Depth 0.04, 0.02, 0.06
Vt Adjust Dose 4e+12, 2e+12, 6e+12

Table 1. A summary of the variables and values used in the VWF experiment.


The spread of the output current is shown in Figure 2. The forward Vt can be very small for some combinations of Vt adjust dose and recess depth. These low Vt devices will correlate with the high output current devices.

Figure 2

Figure 2. Variation in Output Drive Current with different process conditions.

Visual inspection of such curves yields useful ranges for possible optimization and since the entire curve is presented, other parametrics can be estimated which were perhaps not extracted in the experiment. In order to fully evaluate and optimize these characteristics, a response surface model (RSM) was constructed using the VWF RSM modeling tool. The characteristics will be separated into channel engineering and layer scaling.

Figure 3 shows the effect of Vt adjust implant dose and recess depth on forward Vt for a fixed buried oxide layer thickness. Figure 4 shows the back gate threshold voltage as a function of recess depth and BOx thickness for a fixed implant


Figure 3
Figure 4
Figure 3. Variation in forward Vt for a fixed BOx thickness. Figure 4. Variation in back gate Vt as a function of layer thickness.

In order to determine optimum layer thickness, Figure 5 displays the relationship of forward and back Vt on the active silicon and buried oxide layers for a fixed Vt adjust implant dose. It can be seen that reasonable forward Vt's and large reverse Vt's can be obtained even for thin devices.

Figure 5

Figure 5. Forward and Reverse Vt as a function of layer thickness'.
The vertical axis shows the forward Vt and the shading shows the back gate Vt.

Missing from the previous analysis is the dependence of output drive current on these parameters. Figure 6 combines Idsat with forward Vt. It can be seen that the output current drive has a weak dependence on the buried oxide layer thickness. This decouples buried oxide thickness from the output drive current and allows back Vt optimization to be handled separately.

Figure 6

Figure 6. Saturation current and forward Vt
as a function of silicon and Box thickness.

From Figure 7, it is seen that it is possible to have both reasonable forward Vt and decent output drive current without resorting to too thin an active silicon layer or too high a Vt adjust implant dose. Very thin active silicon layers can cause current reduction due to increased Rds. High Vt adjust implant doses can severely effect the back Vt of the device.VWF has been used to analyze the trade-offs in optimizing an RC SOI technology. Forward Vt, back Vt, and Idsat were seen to be dependent on layer thickness for the region of operation covered. The importance of scaling Vt adjust implant dose with active silicon layer thickness was also demonstrated.

Figure 7

Figure 7. Saturation current and forward Vt as
a function of Vt adjust dose and silicon film thickness.


VWF experimentation on a recessed SOI structure has been used to produce behavior models of forward and back gate Vt as functions of channel implant dose and layer thickness'. Analysis of these models can be used in channel engineering studies to maximize Idsat while maintaining back gate Vt at an acceptable level.