Transient Simulation of CMOS Device Latch-up

Simulation of the latch-up of the parasitic pnpn structure in CMOS technology has traditionally been very time consuming. The models and numerical techniques required to give accurate results for transient latch-up is one factor. However the overriding problem is that the structures are large in scale yet require a fine resolution in certain locations. This leads to large grids and hence to long simulations.

The example presented here demonstrates the simulation of latch-up in an twin well CMOS process generated by ATHENA. The geometry of the contacts and wells were taken from an IC layout using MASKVIEWS (Figure 1). With MASKVIEWS it is possible to use a single ATHENA input file to describe the process flow. If the n+/p+ spacing is varied in the layout this will automatically be transferred into the process simulation. The final structure is shown in Figure 2. As an initial condition the pwell and Vdd contacts are biased to 5V and the Vss and nwell contacts are grounded.

Figure 1. Layout and mask cross-section for a CMOS well boundary. This is used as input t ATHENA.

Figure 2. CMOS Latch-up structure at initial biasing conditions.

There are two ways to initiate latch-up in CMOS structures. One is to apply a positive voltage greater than 5V to the Vdd contact. The other condition is to apply a negative voltage to the Vss contact. The latter approach is used here. It is possible to simulate latch-up in DC mode by applying a biasing ramp to the Vss contact. The CURVETRACE command in ATLAS could then be used to trace out the complex I-V characteristic. However In this case a transient approach is used. A negative voltage pulse of 2V was applied to the Vss contact for a period of 2 nano seconds.

Figure 3 shows the resultant transient currents through each contact. Initially the -2V pulse forward biases the diode between the Vss and pwell contacts. At around 1ns the voltage locally within the pwell near the nwell junction drops sufficiently to turn on the lateral pnp transistor between the Vdd, nwell and pwell contacts. In Figure 4 the current flow is seen after 2ns. Eventually the npn transistor between the Vss, pwell and nwell also turns on. After 2ns the Vss voltage returns to zero however the voltages induced by the parasitic resistances within the structure are sufficient to keep the structure latched. Figure 5 shows the current flow in the fully latched structure.

Figure 3. Transient latch-up curves. The VDD to VSS current increases even after the transient voltage pulse is over.

Figure 4. Current flow after 2ns. A significant Vss to pwell current flows.

Figure 5. Current flow in the fully latched CMOS structure.

Studies with different negative pulse heights and widths can be done to determine the trigger conditions for latch-up in a given structure. Alternatively the n+/p+ spacing can be adjusted in the layout and the process repeated to generate design rules.

Figure 6 shows a separate study of the effect of pulse width on latch-up . The CMOS structure used was the same as Figure 2. However a -1V pulse was applied to the Vss contact. Pulses of duration 1ns and 3ns were done is separate runs. the results showed lachtup for the 3ns pulse, whoever the 1ns pulse was not sufficient to trigger latch-up. The Vss to pwell current was not high enough after 1ns to turn on the parasitic npn device.

Figure 6. Effect of Vss pulse width on latch-up. A 1ns pulse is insufficient to latch the structure.

The reduction in execution time by using parallel ATLAS on this application is shown in Figure 7. A higher than average efficiency of parallelization is seen. This is expected since optimal parallelization occurs when a dense mesh is present.

Figure 7. Execution time improvement with number of processors for CMOS latch-up simulation.