Low Power MOSFET Modeling Devices Using the EKV Model


The current trend towards low-power circuit design has focused much attention on the ability of available MOS models to accurately characterize devices operating in the weak or moderate-inversion regions of device operation. Some of the more recent commercial MOSFET models have attempted to address this issue with various degrees of success. UTMOST currently supports the extraction of parameters for the BSIM1, BSIM2, BSIM3, and Philips Level 9 MOSFET models. Proprietary models can also be dynamically linked to UTMOST. The Enz-Krummenacher-Vittoz or EKV model [1] is another model targeted at analog circuit design applications. This model has been implemented into UTMOST as a so-called dynamically-linked model. This article will detail the EKV model and describe how parameters can be extracted for this model in a very simple manner. Examples of the extraction of n-channel and p-channel parameter sets will be detailed. Customers who wish to evaluate this model can do so by contacting SILVACO so that the required model libraries can be supplied.


The EKV Model

The requirements of a good MOSFET model suitable for analog applications are well documented [2,3]. The EKV model claims to satisfy most of these criteria. In addition, the EKV model is hierarchically structured, offering several coherent hierarchical levels, from simple analytical expressions to support creative synthesis, to more detailed expressions for precise computer simulation. The simplicity and intuitiveness of the EKV model helps the circuit designer to understand the operation of the MOS transistor and to correctly exploit and master its various characteristics in order to develop new high performance circuits. A detailed description of the static and dynamic model formulations including temperature and noise models is available elsewhere [4]. For parameter extraction purposes, the model basically consists of only nine core physical parameters, two temperature parameters, and three second-order fitting parameters. The model exhibits continuous simulated currents, conductances, intrinsic capacitances, and non-quasi-static transadmittances in all regions of device operation. The modeling of the weak and moderate-inversion regions of operation received particular attention during the formulation of the EKV model.


Parameter Extraction Example

In this example an attempt was made to extract EKV model parameter sets for single NMOS and PMOS devices. The devices under analysis had drawn widths of 20um and drawn lengths of 2um. These devices were fabricated with a 0.5um CMOS process. The UTMOST ALL_DC routine was used to measure (a) a family of IDS-VGS curves where VDS was set to +/- 0.1V and VBS was stepped between 0V and -/+ 1.6V and (b) a family of IDS-VDS curves where VBS was set to 0V and VGS was stepped between VTH +/- 0.2V and +/- 3.6V.


Parameter extraction was accomplished by means of the general purpose local optimization facility in UTMOST. It was only necessary to extract values for eight model parameters. Five of these were extracted from the linear-region IDS-VGS curves while three more were extracted from the measured IDS-VDS curves and the derived GDS-VDS curves. The parameter extraction strategy which was utilized is detailed in Table 1.

Data Used Min Limit Max Limit Parameters Extracted
1 IDS-VGS (VBS=0V) 7% 100% VTO, THETA, and KP
2 IDS-VGS (@VBS) 5% 15% GAMMA and PHI
3 IDS-VDS & GDS-VDS 1e-8 1e0 LAMBDA, UCRIT, and XJ

Table 1. Sample EKV parameter extraction strategy.


Note: For UTMOST local optimization procedures, the minimum or maximum optimization target limits can be specified absolutely (see Stage 3) or as percentages of the maximum measured characteristic for any measurement sweep (Stages 1 and 2).

The resultant measured and simulated device characteristics are shown in Figure 1 and Figure 2. The linear region IDS-VGS data for NMOS and PMOS devices is shown in Figure 1. Figure 2 shows IDS-VDS data, GDS-VDS data, and subthreshold IDS-VGS data. It can be seen that the extracted model can predict the threshold voltage and body effect for both device polarities but the model fails to accurately predict low-field device mobility for non-zero substrate biases. The modeling of the weak and moderate-inversion region IDS-VGS data is excellent, especially considering the fact that it was not necessary to perform any parameter extractions to this region of device operation. The prediction of the moderate and strong-inversion region IDS-VDS and GDS-VDS data is also very good even though only three parameters need to be extracted. The model exhibited smooth and continuous predictions of device current and conductance in the troublesome transition regions (i.e. in the moderate inversion region for the IDS-VGS data and in the transition between linear and saturation for the IDS-VDS and GDS-VDS data).


Figure 1. Measured and simulated IDS-VGS characteristics for
(a) the 20/2µm NMOS device and (b) the 20/2µm PMOS device.

Figure 2. Measured and simulated IDS-VDS and GDS-VDS characteristics as well as subthreshold IDS-VGS characteristics for (a) the 20/2µm NMOS device and (b) the 20/2µm PMOS device.



The EKV MOSFET model has been linked to the UTMOST parameter extraction tool using the new dynamically-linked model facility. The EKV model was formulated for use in low-current and low-voltage analog circuit applications and features smooth and continuous predictions of currents and conductances in all regions of device operation. A simple parameter extraction strategy, employing local optimization techniques, was implemented in UTMOST for the EKV model. The results of parameter extraction examples for both NMOS and PMOS devices proved to be very encouraging and yielded acceptable models for low-power circuit applications. The model, and thus the parameter extraction procedure, are both intuitive and simple. These are very important considerations if circuit designers are to exploit the maximum benefit from their circuit simulator device model-of-choice.



Silvaco would like to thank Christian Enz and Matthias Bucher from the Swiss Federal Institute of Technology, Lausanne, Switzerland for their invaluable help during the preparation of this article.



  1. G.A.S. Machado, C.C. Enz, and M. Bucher
    "Estimating key parameters in the EKV MOST model for analogue
    design and simulation," proc. of IEEE ISCAS'95.
  2. Y. Tsividis and G. Masetti, "Problems in precision modeling
    of the MOS transistor for analog applications" IEEE Trans. on Computer-Aided Design, vol. CAD-3, pp. 72-79, Jan. 1983.
  3. Y. Tsividis and K. Suyama
    "MOSFET Modeling for analog circuit CAD:problems and prospects"
    IEEE Journal of Solid-State Circuits,
    vol. SC-29, pp. 210-216, March 1994.
  4. C.C. Enz
    "MOS transistor modeling dedicated to low-current and low-voltage analog circuit design and simulation" proc. of the IVth Brazilian School of Microelectronics, 1994.