Accurate Worst-Case Model Generation with SPAYN



Statistical fluctuations inherent in any IC manufacturing process cause unavoidable variations in device and circuit performance. These circuit performance variabilities can cause serious yield and reliability problems if they are not accounted for at the circuit design stage. It is imperative that the so-called statistical nature of any process is determined so that costly re-design cycles are avoided. Accurate worst-case model parameter sets need to be generated. In addition, efforts must be made to define the relationships between the variations in circuit simulator model parameters and the core process variabilities which cause them. SPAYN is Silvaco's statistical parameter analysis and worst-case modeling package. It is the ideal tool for accomplishing these all-important tasks.

SPAYN can accept data from Silvaco's UTMOST and Virtual Wafer Fab (VWF) packages. E-test, parameter extraction, or circuit test parameters originating from other sources can also be read into SPAYN quite easily.

SPAYN will perform data filtering, generate short-form parameter statistics and diagnostics, prepare histograms and scatter plots, construct correlation matrices, perform principal component analyses (PCA) or principal factor analyses (PFA) to determine key independent process-related variables, display process monitor or process control charts, determine "corner" models or correlated Monte Carlo models, and directly drive selected circuit simulations in order to isolate worst-case model parameter sets [1,2].

SPAYN makes the task of generating realistic and accurate process corner models very easy. SPAYN will also communicate with commercial circuit simulators including SmartSpice so that the worst-case model parameter sets associated with any particular circuit application can be determined automatically. By merging model parameter information with E-test data, the SPAYN user can relate model parameters, parameter variabilities, and parameter correlations to process monitor variables which are routinely measured.

SPAYN enables specific circuit performance variations to be linked to the process-related parameters. The effects on the circuit, of tightening or loosening the controls on these process variables, can also be easily determined. Using data generated by a combination of UTMOST and VWF, process corner or worst-case model parameter sets can be generated for a process under development. This topic will be the subject of future Simulation Standard articles.



Model parameters for the Berkeley Level 3 MOSFET model were extracted, over a period of time, from over 1000 sites on a 1µm CMOS process. Complete sets of n-channel and p-channel parameters were collected on each site. These parameter sets were read into SPAYN where preliminary analyses were performed to determine suitable parameter distributions and eliminate parameter sets containing troublesome outliers. Statistical summary tables, histograms, and scatter plots were generated (see Figure 1).


Figure 1a. Example of a parameter histogram generated by SPAYN.


Figure 1b. Example of a scatter plot generated by SPAYN.



A principal component analysis was performed on the 27 correlated model parameters using an 80% variance retained criteria. It was found that 6 independent components explained almost 81% of the variance of all of the original model parameters. Each of these 6 components was then replaced by the model parameter with which it was most correlated (i.e. its dominant parameter). Equations were generated relating each of the non-dominant parameters to the independent dominant parameters.

In this case, the dominant parameters were found to be p-channel THETA parameter (19.7% variance), p-channel LD (19%), n-channel UO parameter (12.9%), n-channel NFS parameter (10.3%), n-channel KAPPA parameter (9.7%), and p-channel WD parameter (9.2%). The identity of the independent dominant parameters can be changed by the user if required. The process line-width, thickness, implant, and diffusion variations related to each of these dominant parameter variations were readily identified. Some examples of the equations generated in this example are shown below:


THETA_P = X1, LD_P = X2, U0_N = X3, NFS_N = X4,
KAPPA_N = X5, WD_P = X6

VT0_N = - 3.3626*X1 + 2.8326e+05*X2 + 0.00017834*X3 +
3.359e-13*X4 - 0.025885*X5 - 1.0936e+05*X6 +1.2914

GAMMA_N = - 2.8588*X1 + 89359*X2 + 0.00057294*X3 +
7.1788e-14*X4 - 0.0054537*X5 - 26142*X6 +0.72371

VMAX_N = 47071*X1 - 3.3022e+10*X2 + 358.33*X3 -
1.8654e-08*X4 + 1.677e+05*X5 - 3.3146e+10*X6 -56801

THETA_N = 0.48237*X1 - 5450.5*X2 + 4.5235e-05*X3 -
5.0786e-15*X4 + 0.00060434*X5 + 1812.6*X6 -0.043298



The 6 dominant parameters, and the system of equations derived in order to calculate the remaining dependent parameters, were used as a basis for the generation of a process monitor chart (see Figure 2) and accurate process corner models. For this example, full CMOS Level 3 parameter sets, corresponding to all combinations of the dominant parameters set to +/-3o, were generated. There were a total of 64 of these corner models for the case of 6 uncorrelated dominant parameters. Other parameter set generation possibilities including the generation of a correlated Monte Carlo parameter set are also offered as options by SPAYN.


Figure 2. SPAYN process monitor chart showing
batch-averaged dominant parameter values (the limits shown for each parameter are the +/- 1o,
2o, and 3o parameter limit from the entire sample.


SPAYN was then linked to a circuit simulator using the VYPER environment and various test circuits were simulated using the corner models (see Figures 3 and 4). From these simulations it was possible to identify good worst-case model parameter sets for different circuit applications, where the model parameter limits were realistic, and parameter correlations were accounted for correctly. The effects of changing the control on process variabilities can also be easily assessed.


Figure 3a. CMOS inverter transfer characteristics
using all process corner models.


Figure 3b. CMOS inverter trigger current
characteristics using all process corner models.



Figure 4. Ring oscillator (11-stage) circuit
characteristics using all process corner models.




Silvaco would like to thank Barry Mason and Paul Stribley of GEC Plessey Semiconductors, Roborough, England, and Rory Clancy and Kevin McCarthy of the National Microelectronics Research Centre, Cork, Ireland, for their valuable contributions. The data used in this article was supplied by GEC Plessey Semiconductors, from their 6" wafer fabrication plant in Roborough, U.K., and came from the production 1.0¨µm CMOS analog process.



[1] J. A. Power, B. Donnellan, A. Mathewson, and W. A. Lane, "Relating Statistical MOSFET Model Parameter Variabilities to IC Manufacturing Process Fluctuations Enabling Realistic Worst-Case Design," IEEE Trans. on Semicond. Manufact, vol.7, no.3, pp. 306-318, Aug. 1994.

[2] M. Bolt, M. Rocchi, and J. Engel, "Realistic Statistical Worst-Case Simulations of VLSI Circuits, " IEEE Trans. Semicond. Manufact., vol.4, no.3, pp. 193-198, Aug. 1991.