Analog Behavioral Simulation Using SmartSpice
Dr. J.J.Charlot, J.P. Nkolo
(TELECOM, Paris), and
Dr. A. Zavorin, J. O'Donovan, M.D. Bennett and Dr. A. Tcherniaev
(Silvaco International)
Introduction
In recent years, Hardware Description Languages (HDL) such as VHDL or Verilog HDL have become industry standards for digital system simulation. These languages provide excellent behavioral capabilities, which allow simulation time to be reduced drastically and entire systems to be simulated. With the increasing complexity of analog and mixed analogdigital circuits, the limitations of the traditional SPICEtype analog simulation approach has become obvious.
The physically based SPICE component models, while providing much detail about device and circuit behavior, consume large amounts of memory and CPU time, thus limiting the size of the simulated circuit to several thousand components. One of the possible solutions to this problem is to employ a mixed level analogdigital simulation approach (see October '94 issue of The Simulation Standard). This approach is adequate for digital systems which contain a few critical analog parts. In this case the system can be successfully simulated with a combination of the digital HDL simulator and SPICEbased analog simulator. Nevertheless, this approach does not remove the limitations which the traditional analog simulation techniques impose upon the analog portion of the system. By providing analog behavioral modeling capabilities within SmartSpice such CPU, time and memory limitations can be reduced.
A number of different approaches to analog behavioral simulation in SPICE currently exist. The first one is to use socalled dependent sources (voltage and current). This approach has been derived from Berkeley SPICE and is supported by SmartSpice. Silvaco has improved and enhanced the capabilities of dependent sources, resulting in what are now referred to as arbitrary sources.
Another approach is to allow the user to add device models to SPICE through an interface to internal SPICE data structures. In this case, the user has to describe this model using the C programming language, compile this code and link the resulting object files with the rest of the SPICE code. Silvaco now provides the most advanced interface to user Clanguage models through the SmartSpice Model Interpreter. When using the Interpreter, the model code does not have to be compiled by the user but can be loaded directly into SmartSpice.
However, the nature of analog behavioral simulation imposes some special requirements which make the C programming language inconvenient for such tasks, making it necessary to develop special analog HDL languages.
Silvaco has closely monitored the efforts of the IEEE 1076.1 committee in establishing the analog VHDL standard (VHDLA) since its formation in 1993. In mid 1994 a decision was made to start development of analog VHDL capabilities in SmartSpice prior to the official release of the VHDLA standard.
The SmartSpice VHDLA interface is currently being tested and is scheduled for release in the second quarter of 1995.
This article illustrates new SmartSpice capabilities in analog behavioral simulation.
Behavioral Modeling using Arbitrary Sources
The concept of dependent sources in traditional SPICE simulators has been extended in SmartSpice with the addition of a new device, the Arbitrary Source. This device allows much more comprehensive modeling of the behavior of both analog and digital circuit elements, in addition to nonelectrical components, e.g. mechanical elements.
An arbitrary source allows the user to describe the voltage across or current through the device in terms of an expression. This expression can contain references to and functions of node voltages, device currents and user parameters. All the standard mathematical functions available in dependent source expressions can be used.
TIME, TSTEP and TEMP Parameters
Arbitrary source expressions have been extended so that the current time, timestep and temperature at which simulation is being performed can be used. From the user's viewpoint, these new variables, 'TIME', 'TSTEP' and 'TEMP' respectively, can be treated as normal user parameters.
Hence, for example, a simple model of a diode can be created using the following equation for the current through the diode;
Idiode = Is . (e  1) where Is = diode saturation current, VT = thermal voltage (kT/q), and Vdiode = voltage across the diode.
A diode can then be modeled using an arbitrary source as follows;
.PARAM Is = 1.0E14
.PARAM KoverQ = 8.617e5
.PARAM Vt = 'KoverQ * (TEMP + 273.15)'
Bdiode out 0 I= Is * (EXP (V(out) / VT)  1.0)
IFTHENELSE Conditions
Since the behavior of many circuits, especially digital circuits, will depend upon certain conditions, expressions within an arbitrary source have been extended to contain inline IF conditions. For example, in order to ensure that current through the diode in the previous example is 0.0A when the voltage across the diode is negative, the following arbitrary source expression could be used;
Bdiode out 0 I= IF V(out) < 0.0 THEN  
+  0.0  
+  ELSE  
+  Is * (EXP (V(out) / VT)  1.0)  
When Vout is negative the current through the source is 0.0A, otherwise it will be computed using the diode equation.
The time and temperature parameters can also be used within conditions. For example, the following source will generate a decaying sinusoid waveform which has a frequency of 4MHz prior to 20µs and 1MHz for all times greater that 20µs, as shown in Figure 1.
B1 out 0 V= IF TIME >> 20u THEN  
+  EXP ((TIME  20u) * 0.5MEG) * SIN (6.28 * 
+  1MEG * (TIME  20u)) 
+ ELSE  
+  EXP (TIME * 0.25MEG) * SIN (6.28 * 
+  0.25MEG * TIME) 
Figure 1. Top figure shows decaying
sinusoid. Bottom figure
shows decaying sinusoid in top figure delayed by 25µs.
Derivatives
Modeling the behavior of analog components often results in expressions containing derivatives and integrals. In order to model these elements more effectively, it is now possible to include derivatives of node voltages and device currents with respect to time within expressions, using the 'DER.' operator. For example, if the equation describing the behavior of a nonlinear capacitor is as follows;
Ic = C (1 + ABS (Vc)) * dVc/dt
then this device can be modeled using the following arbitrary source;
Bcap n 0 I= C * (1.0 + ABS (V(n))) * DER.V(n)
Another example involves the modeling of mutual inductance. The traditional approach involves the use of inductors and a mutual inductance element which allows the coupling between the inductors to be specified. If two inductors LA and LB are coupled and their mutual inductance is M then the following netlist portion will describe their behavior;
LA N 0 l1 LB M 0 l2 KAB LA LB k
The KAB element indicates that the inductors LA and LB are coupled and that the mutual coupling coefficient is k. This coefficient is calculated by the user using the mutual inductance M and the inductance of the elements which are coupled according to the equation;
k = M / SQRT (l1 * l2)
For transient analysis, the equations describing the voltages across the inductors are as follows;
= Va = l1 * dI1/dt + M * dI2/dt and Vb = M * dI1/dt + l2 * dI2/dt
Hence, using arbitrary sources, the behavior of mutual inductors can be modeled using the following arbitrary sources;
B1 N 0 V= l1 * DER.I(B1) + M * DER.I(B2) B2 M 0 V= M * DER.I(B1) + l2 * DER.I(B2)
Arbitrary Source Delays
When modeling the behavior of some designs, voltage values calculated at previous timepoints must be stored for use in expressions. This is especially important when modeling digital components. For this reason two special arbitrary sources have been introduced. The first is a simple delay type source which causes the voltage at the controlled node to be the same as that of the controlling node except that it will be delayed by a specified time. For example, the arbitrary source in the following example will cause the voltage at node out to be the same as that at node in except that it will be delayed by 25µs.\
B1 in out DELAY=25u
The result of applying the decaying waveform shown in Figure 1(top) to this arbitrary source is given in Figure 1 (bottom).
The second delay type arbitrary source causes the voltage at the controlled node to be the same as that of the controlling node at the previous timepoint in the simulation, i.e. at time TIME  TSTEP. This is especially useful for modeling circuits such as phase lock loops.
Digital Modeling
Using arbitrary sources with IFconditions, it is possible to model the behavior of a wide variety of digital components. Digital elements can be designed to include delays, using the DELAY type arbitrary source, discussed previously. A simple behavioral model of the OR gate is given in the following subcircuit;
.SUBCKT OR a b out
B1 out1 0 V= (ABS (V(a)  V(b)) + V(a) + V(b)) / 2
B2 out1 out DELAY = 5n
ENDS
The inputs to the OR gate are a and b. It is assumed that the voltage range is from 0V to 1V, although this can be scaled to any voltage range if necessary. This model results in an output voltage of 1V if either input is high (1V) and 0V if both are low (0V). There is a linear transition between 0V and 1V if the inputs are neither 0V or 1V. There is a delay of 5ns, provided by B2, between a change in the input voltages and the corresponding output voltages.
Analog VHDL Models in SmartSpice
The analog VHDL models in SmartSpice use the SmartSpice CInterpreter. A special VHDLA translator will convert VHDLA code into C code, suitable for direct loading into SmartSpice. This code can also be compiled using the regular C compiler to produce a dynamic library, which will be automatically loaded in SmartSpice. The first option allows for the quick and seamless use of VHDLA models in SmartSpice. This is especially important in the development phase of a model, while the second option can be used to compile large VHDLA libraries of components, thus maximizing simulation speed.
VHDLA models can be used anywhere in SmartSpice input decks as a special element  Y devices.
One of the problems which makes the development of new SPICE models difficult, is the need to supply the model in the form I = f(V) (where I is the vector of the terminal currents and V is the vector of terminal voltages) along with the matrix of all possible derivatives of terminal currents with respect to terminal voltages (conductance/transconductance matrix). The calculation of the conductance matrix for complex models can be quite difficult.
The use of VHDLA models eliminates the need for derivative calculation since the SmartSpice VHDLA translator automatically calculates required derivatives in symbolic form and adds them to the generated C code.
The following example illustrates the use of a VHDLA model in SmartSpice. It is a VHDLA implementation of the simplest DC MOSFET model (which is similar to the SPICE Level 1 model).
The VHDLA input file describing the model is shown in Figure 2. The SmartSpice input deck which calls this model is shown in Figure 3. This input deck produces the family of ID/VD curves, shown in Figure 4.
PIN (drain, gate, source, bulk : electrical); 

GENERIC( 

K: real 
:= 1.0e3; 

lambda : real := 1.0e2; 

gamma : real 
:= 0.8; 

phi : real 
:= 0.65; 

vt0 : real 
:= 0.7); 

CONSTANT (qe : real := 1.6e19; bk : real := 1.33e23); 

VARIABLE (vt : real); 

STATE(vds, vgs, vbs, cds : real); 

PROCEDURAL FOR init => 

lambda 
:= 1.0e3; 

K 
:= 1.0e3; 

vt0 
:= 0.7; 

gamma 
:= 0.5; 

phi 
:= 0.65; 

PROCEDURAL FOR dc => 

lambda 
:= 1.0e3; 

K 
:= 1.0e3; 

vt0 
:= 0.7; 

gamma 
:= 0.5; 

phi 
:= 0.65; 

PROCEDURAL FOR dc => 

vds 
%= (drain, source).v; 

vgs 
%= (gate, source).v; 

vbs 
%= (bulk, source).v; 

cds 
%= (drain, source).i; 

vt 
%= vt0 + gamma * ( sqrt(phivbs)  sqrt(phi) ); 

IF (vgs <= vt) THEN cds %= 0.0; 

ELSEIF (vds <= vgsvt) THEN 

cds 
%= K*vds*(vgsvt  0.5*vds)*(1.0 + lambda*vds); 

ELSE 
cds %= 0.5*K*(vgsvt)*(vgsvt)*(1.0 + lambda*vds); 

END IF; 
Figure 2. A VHDLA DC MOSFET model.
******* mos_id_vd ******* vd1 1 0 dc 5 vg1 2 0 dc 4 vb1 5 0 dc 0 YM1 4 0 3 2 0 5 mos userparams = model_parameters r1 1 3 0.01 .dc vd1 0.0 5.0 0.1 vg1 1 5 2 .PRINT DC I(R1) v(2) v(1) .model mos NTYPE ( + userparams = model_parameters + dcsourcecode = y_model_dc.int dcfunction = y_model_dc + ) .END
Figure 3. The SmartSpice input deck which uses VHDLA model
Figure 4. The family of IDVD produced using VHDLA MOSFET models.
Summary
Analog behavioral simulation becomes important for the design of large analog and analog/digital circuits. SmartSpice provides an effective solution for this, using both the traditional methods and stateoftheart techniques based on the emerging VHDLA standard. The implementation of VHDLA simulation capabilities in SmartSpice preserves the investment in the development of conventional SPICE models, while also allowing a smooth transition to the new simulation technology.