Single-Event Gate-Rupture in Power MOSFETs:


Prediction of Breakdown Biases and Evaluation of
Oxide Thickness Dependence


© 1995 IEEE. Reprinted, with permission, from IEEE Transactions on Nuclear Science, Vol.42, December 1995.

M. Allenspach1, I. Mouret1,2, J.L. Titus3, C.F. Wheatley, Jr.4 ,
R.L. Pease5, J.R. Brews1, R.D. Schrimpf1, and K.F. Galloway1
1 The University of Arizona, Tuscon, AZ 85721
2 Aerospatiale, Les Mureaux, France
3 Naval Surface Warfare Center - Crane, IN 47522
4 RR2 Box 1120,, Drums, PA 18222
5 RLP Research, Inc., Albuquerque, NM 87122




Single-Event Gate-Rupture (SEGR) in Vertical Double Diffused Metal-Oxide Semiconductor (VDMOS) power transistors exposed to a given heavy ion LET occurs at a critical gate bias that depends on the applied drain bias. A method of predicting the critical gate bias for non-zero drain biases is presented. The method requires as input the critical gate bias vs. LET for VDS = 0V. The method also predicts SEGR sensitivity to improve for larger gate-oxide thicknesses. All predictions show agreement with experimental test data.



Single-Event Gate-Rupture can lead to power MOSFET failure in space. The SEGR process is initiated when a heavy ion strikes the device in the neck region. The neck region is the area between the p-body diffusions at the surface (see Figure 1). The ion strike creates a filament of electron-hole pairs. For an n-channel power MOSFET, the generated holes drift toward the interface and the electrons toward the drain contact due to the electric field resulting from the positive drain bias. Upon reaching the interface, the holes start to `pile up' at the interface and `leak off', only slowly, toward the source contact. This pool of positive charge increases the electric field in the oxide, and when the field exceeds a critical value, oxide breakdown occurs. The collected holes then discharge through the oxide, heating the structure locally. If the breakdown current lasts long enough, a permanent short-circuit through the oxide results.


Figure 1. One half of the cross section of the stripe geometry
n-channel test device used in the experiments. For simulations, the
device was approximated in cylindrical geometry to avoid
time consuming 3-D computations.



While progress has been made in empirically describing SEGR and modeling the mechanism [1]-[5], its dependence on structural parameters has not been elucidated. In this work, a simple model that utilizes two dimensional ATLAS[1] simulations to predict SEGR breakdown condition for a given heavy ion LET is introduced. The predictions were used to investigate SEGR dependence on oxide thickness, LET of the incident ion, and the VGS versus VDS interrelation at rupture. A ``base-line'' cross section of the devices used in the 2-D simulations and in the experiments is illustrated in Figure 1. Device details for the simulated VDMOS transistors were based on SSuprem4 [2] profiles for stripe geometry test structures that were built for experimental verification of oxide thickness dependence. The experimental data are reported fully elsewhere[3]. The following sections will further discuss the SEGR mechanism, present a methodology for predicting SEGR, and illustrate the excellent agreement between the prediction technique and experiment.


Prediction Methodology

In order to evaluate SEGR hardness of power DMOS transistors, it is common practice to find the threshold biasing condition in a given radiation environment (LET of incident ion given). Operating a DMOS device below this threshold biasing conditions (VDS, VGS) guarantees safe operation whereas exceeding this threshold will result in gate rupture and, thus, destroy the DMOS transistor. One method to find these threshold biasing conditions is an experimental approach (see [2], [3]). However, these experiments are usually rather costly and time consuming. In this paper, we will show an alternative method to derive these threshold bias conditions by combining a fast and inexpensive prediction algorithm that utilizes 2-D simulation results (PISCES simulations) with measured oxide breakdown strength Ecr vs. LET data for VDS = 0V. The method is based upon



where VGScr = critical gate-to-source bias for SEGR, Etrmax = maximum transient oxide field from 2-D simulation for VDS 0, Ecr = experimental input for VDS = 0, and dOX = oxide thickness. Each of these components is now to be described in detail.


Modeling the Transient Oxide Field (VDS0)

SEGR dependence on LET, gate-oxide thickness, and VGS versus VDS interrelation in VDMOS n-channel power transistors was investigated through 2-D simulations. For all simulations, the ion was assumed to traverse the device at normal incidence through the center of the neck region. In the simulations, we used cylindrical geometry and generated the charge due to the passing energetic ion as a charge cylinder with a Gaussian lateral distribution of characteristic length L = .07µm and uniform distribution in depth. Details of the simulation of the ion track are given in the Appendix.

An example of the transient oxide field obtained from 2-D simulations is shown in Figure 2. Input data supplied by a user for the simulation includes structural dimensions of the test device, energy and spatial information of a traversing ion, and bias conditions for the device. The simulator then computes various physical quantities including potential distribution, electric fields, and carrier concentration profiles. The result of practical interest is a critical biasing condition for a VDMOS device that leads to SEGR (for a given LET value of the incident ion). A difficulty in applying our 2-D simulation results is that no oxide breakdown model is included in the simulations. We now describe how we have dealt with this problem.


Figure 2. Transient oxide field component at track location
superimposed on DC component as a function of time after
ion strike for bromine and gold as the incident ions.
Typically, the peak field is reached within a few picoseconds.
Parameters: LET=37.2 (Bromine) and 82 (Gold)
MeVcm2 /mg, VGS=-13.9V, VDS=30V, dOX=50nm.


If we assume the total charge generated in the oxide is small compared to the filament charge in the silicon, then the electric field in the oxide is the sum of a transient field component due to substrate charge collection effects (related to VDS [1]) plus a DC field component due to VGS (see equation (2))

The DC part of the oxide field EDC can be calculated with the simulator for any given biasing condition when there is no ion strike (zero charge generation). EDC is approximately (neglecting work function differences)

For sufficiently negative VGS values (in n-channel devices), there is no dependence of EDC on VDS because the surface is inverted and the inversion layer places the Si/SiO2 -interface on the same equipotential as the grounded body contact [4]. The simulated transient component of the oxide field, Etr, reaches its peak value within a few pico seconds after the charges due to the traversing ion are generated (see for example Figure 2). The transient field persists for a time of about 50ps which varies somewhat with LET and VDS.

One might expect that oxide transients of such short duration would not be as fully effective as a DC oxide field in causing SEGR. However, comparison of 2-D simulations at biasing conditions where SEGR was detected experimentally with experimental results indicated that failure occurs when the transient oxide field exceeds a critical value, Ecr, made up of any combination of DC and transient components.

Using equation (5) for the LET-dependence of Ecr, and the empirical assumption that transient and DC oxide field contribute on the same basis to Ecr, it is simple to predict a critical gate-to-source bias VGS=VGScr that initiates SEGR for a given heavy ion LET and a given drain-to-source bias VDS > 0.


DC Input Data (VDS = 0)

For DC applied fields and for normal incidence of the ion, Wrobel [5] measured the dependence of Ecr on the ion's LET value. Equation (4) is Wrobel's empirical fit to experimental breakdown data on heavy-ion irradiated MOS-capacitors,

where LET is in MeV cm/mg and Ecr is in MV/cm. This fitting function is inaccurate for low LET values where it predicts that Ecr is infinite as the LET value approaches zero. A better fit to the data that agrees with the intrinsic breakdown value of Ecr =E0 for LET values of the incident ion approaching zero is,

where LET and B is in MeV cm/mg and Ecr and E0 is in MV/cm. It is usually very difficult to measure the intrinsic breakdown field of a gate-oxide (LET=0) using MOS devices because the oxide usually tends to break down at a lower field strength at a defect related weak spot of the oxide. The breakdown location for irradiated oxides, on the other hand, will be at the strike location that usually does not coincide with a weak spot of the oxide. Therefore, to extract dielectric breakdown data of the gate-oxide (Ecr vs. LET), the breakdown field for LET=0 will not be measured but extrapolated by fitting expression (5) through the experimental data points for LET>0. Applying this procedure to Wrobel's [5] experimental breakdown data yields E0 = 11.1 MV/cm and B = 62.1MeV cm/mg. The breakdown strength of different oxides varies somewhat due to different processing steps, and is a necessary input for our prediction algorithm. The solid line in Figure 3 was obtained by fitting equation (5) to the breakdown data for the devices used in this work E0 = 9.1 MV/cm, B = 58.0 MeV cm/mg) The symbols in Figure 3 correspond to experimental data points taken from the stripe line geometry DMOS transistors used in this work.



Figure 3. Inverse breakdown field due to applied
gate-to-source bias VGS versus LET of the incident ion.
Symbols show experimental data on irradiated devices with
VDS=0 and solid line was obtained by a least square
fit of expression (5) to devices with various oxide thicknesses.



Outline of Method

Below, an outline is given that shows how to obtain a prediction for the maximum (critical) gate-to-source bias VGS that can be applied to a VDMOS power transistor for a given heavy ion LET with a specified drain-to-source bias VDS > 0. Exceeding this critical bias VGS will initiate SEGR and cause destruction of the device.

1. Define input deck for 2-D simulator ATLAS including:

  • device geometry and dimensions
  • drain-to-source bias, VDS > 0, where corresponding critical gate-to-source bias, VGS, is sought
  • input parameters for charge distribution along the ion track (apply equations (A7) - (A10) shown in Appendix)
  • arbitrary negative gate-to-source bias, VGS, sufficient to invert the surface (The transient portion of the oxide field due to substrate charge separation computed below does not depend on the choice of VGS at this point.)


2. Run ATLAS

  • find the DC field component EDC (LET=0).
  • initiate charge filament appropriate to the ion LET along ion strike path and continue with a transient simulation to compute oxide field versus time at the strike location.

  • extract the peak field magnitude Ep.

3. Compute peak magnitude of transient oxide field component (at given drain-to-source bias VDS)

4. Compute critical oxide field Ecr for given LET of incident ion from equation (5).

5. Compute critical gate-to-source bias, VGS, (for given VDS and LET) with equation 1.


Simulation Results

Four different gate oxide thicknesses ranging from 50nm to 150nm as used in the experiments [3] were simulated. For every change in oxide thickness, the structure underneath the Si/SiO2-interface was left unchanged and only the thickness of the gate-oxide was adjusted to the desired value. The drain bias VDS was held at a bias of interest and the arbitrary value of the gate-to-source bias VGS was chosen between -6.5V and -28.5V (sufficiently negative to invert surface prior to the ion strike). Simulations were performed for three different incident ions (i.e., Nickel (LET = 26.6 MeVcm/mg), Bromine (LET = 37.2 MeV cm/mg), and Gold (LET = 82 MeV cm/mg) ) and for all the various oxide thicknesses the critical oxide breakdown strength was taken from the data shown in Figure 3. Figure 4 shows four snapshots from the transient simulation to illustrate the spacial migration of the charge filament in time.


Figure 4. The results of the Transient Simulation in four snapshot
windows shows the spacial migration of the charge filament.



Comparison of Predictions with Experiments

All experiments were performed at the Brookhaven National Laboratories (BNL) tandem Van de Graaff facility and are reported fully elsewhere [3]. Figure 5 shows the threshold biases VDS and VGS for a bromine incident ion. The symbols in Figure 5 show experimental data points for five different gate-oxide thicknesses ranging from 50nm to 150nm. The solid lines in Figure 5 were obtained with our prediction algorithm. The predicted threshold biases are in excellent agreement with experimental data for all oxide thicknesses investigated in this work. Figure 6 shows the threshold biases VGS at a drain bias of VDS=30V as a function of LET to further verify the usefulness and potential of this prediction algorithm. Again, the predictions are in excellent agreement with experiments for all three different gate-oxide thicknesses.


Figure 5. VGS versus VDS at rupture point for bromine irradiation
(LET=37.2 MeV cm2/mg) with five different gate-oxide thicknesses.
Symbols are from experiments and solid lines show prediction results.



Figure 6. VGS versus LET of the incident ion at rupture point for VDS=30V
and three different gate-oxide thicknesses. Symbols are
from experiments and solid lines show prediction results.




A simple prediction method for SEGR using a 2-D device simulator was presented. This prediction method utilizes oxide breakdown information (i.e. SEGR data for VDS=0) to predict critical rupture biases (VGS, VDS) for a given heavy ion LET on devices operated at a nonzero drain-to-source bias (i.e. VDS > 0 for n-channel device). Prediction results showing critical threshold conditions to initiate SEGR in DMOS power transistors are in excellent agreement with experimental data. The observed dependence of SEGR on VGS versus VDS, gate-oxide thickness, and the LET value of the incident ion confirm the prediction algorithm.



Equation (A7) shows the mathematical form of the charge distribution, with r = radial direction, where r = 0 corresponds to the center of the track/neck region. Expressions (A8)-(A10) were used to calculate the carrier concentration per unit volume N0 at the track center [7]. The charge distribution of the track is generated uniformly in depth. A more accurate representation of the charge generation along the ion track could be obtained by taking the energy loss of the ion along its path through the device into account. However, extensive 2-D simulations have shown that only the charges generated in approximately the first micron from the Si-SiO2-interface contribute to the collected holes that raise the oxide field.



The charge column due to the traversing heavy ion was ramped up to its final value over a short time interval, t0=1fs. This was achieved by increasing the carrier generation rate constant locally in the track region and running a transient simulation up to t=t0. For t > t0, no further pair generation is allowed, and the electron/hole transport in the substrate is modeled using ATLAS.



[1] J.R. Brews, M. Allenspach, K.F. Galloway, R.D. Schrimpf,J.L. Titus, F. Wheatley, ``A Conceptual Model of Single-Event Gate-Rupture in Power MOSFET's,'' IEEE Trans. Nucl. Sci., vol.40, pp.1959-1966, 1993.

[2] C.F. Wheatley, J.L. Titus, and D.I. Burton,``Single-Event Gate Rupture in Vertical Power MOSFETs; An Original Empirical Expression,'' IEEE Trans. Nucl. Sci., vol.41, pp.2152-2159, 1994.

[3] J.L. Titus, C.F. Wheatley, D.I. Burton, M. Allenspach,J. Brews, R. Schrimpf, K. Galloway, I. Mouret, and R.L. Pease,``Impact of Oxide Thickness on SEGR; Development of a Semi-Empirical Expression,'' to be published in IEEE Trans. Nucl. Sci, December,1995.

[4] M. Allenspach, J.R. Brews, I. Mouret, R.D.Schrimpf and K.F. Galloway, ``Evaluation of SEGR Threshold in Power MOSFETs,'' IEEE Trans. Nucl. Sci.,vol.41, pp.2160-2166, 1994.

[5] T.F. Wrobel,``On Heavy Ion Induced Hard-Errors in Dielectric Structures''IEEE Trans. Nucl. Sci.,Vol.34, pp.1262-1268, 1987.

[6] T. Brozek, B. Pesic, A. Jakubowski and N.Stojadinovic, ``Breakdown Properties of Thin Oxides in Irradiated MOS Capacitors,'' Microelectron. Reliab., vol.33, pp. 649-657, 1993.

[7] S. E. Kerns, ``Transient-Ionization and Single-Event Phenomena,'' Chapter 9, Section 9.1.1, Ionizing Radiation Effects in MOS Devices and Circuits, editors T.P. Ma, P.V. Dressendorfer, John Wiley \& Sons, New York, 1989.



This work was supported by the Defense Nuclear Agency, Naval Surface Warfare Center ­ Crane, NASA ­ Goddard Space Flight Center, Aerospatiale, and Alcatel Escape.7