2D Simulation of Submicron Devices Using Six Equation Physics



Conventional semiconductor device simulators use the drift-diffusion "three equation physics" model consisting of Poisson, electron, and hole continuity equations. This model is an industry "workhorse" for day-to-day device simulation. However, this model can lead to poor accuracy in predicting the electrical characteristics of modern submicron semiconductor devices because non-local hot-carrier transport effects, as well as self-heating effects, are not taken into account.

Most advanced simulation has focused either on isothermal energy balance/hydrodynamic models, for a description of hot-carrier effects, or on non-isothermal drift-diffusion models, for a description of lattice heating. On the other hand, there are obvious examples where the general model with carrier and lattice heating included, should be used for an accurate prediction of the device behavior. For submicron silicon devices, simulation of strong breakdown regime, and simulation of structures obtained with silicon-on-insulator technology could be mentioned as such examples. The need for a general purpose simulator based on "six equation physics" which includes both energy balance and self-heating effects is clear. Such a simulator should be the "workhorse" for the simulation of the next generation of VLSI devices.

The development and implementation of a non-isothermal energy balance model (six equation solver) in the general purpose device simulator ATLAS/S-Pisces is described here. The simulation of submicron LDD MOSFET and ultra-thin SOI devices demonstrates the impact of coupling the self-heating and non-local effects on the electrical characteristics of the device.

Physical Model and Numerical Techniques

The non-isothermal energy balance model (NEB) is a set of six partial differential equations: Poisson's equation for electrostatic potential, the continuity equations for carrier densities (electrons and holes), the electron and hole energy balance equations, and the lattice energy balance equation. The dependencies of all transport parameters on both carrier and lattice temperature are included. The NEB model is an extension of Stratton's energy balance model for the case of non-uniform lattice temperature [1,2].

Numerical solutions are obtained using box integration on a general triangular grid, and Sharfetter-Gummel type discretizations for carrier current and energy flux densities. Several iterative algorithms have been implemented for solving non linear algebraic systems resulting from the discretization. The reason for this is as follows.

A natural and widely used [3,4] decoupled algorithm for energy balance calculations, where Poisson and continuity equations are solved by either Gummel or Newton methods, with the carrier temperatures held constant, followed by the solution of the energy balance equations, has a very slow convergence rate and even fails in some cases, as was shown in [5].

A faster and more reliable algorithm was proposed in the same paper. This algorithm differs from the previous one at the second step: the energy balance equation is solved simultaneously with the continuity equation. Unfortunately, this algorithm also fails for "difficult" situations (e.g. snapback calculations) and the full Newton algorithm is required to handle such conditions [6]. As for NEB simulations, much more difficult conditions could be expected, such as second breakdown calculations [7,8].

The inclusion of the full Newton method in the general purpose device simulator was considered to be essential. However, the efficiency of the Newton algorithm decreases rapidly with the increasing number of mesh points. Therefore, extensions of the block iterative algorithm from [5] were implemented as well. If a block iterative scheme fails to converge after a user-specified number of iterations, the full Newton method is invoked automatically.

Simulation Results

LDD MOS Example

The LDD MOS structure was created in ATHENA. The device had a channel length of 0.3µm and a maximum acceptor concentration in the channel of 2 10 cm . Figure 1 shows Id-Vd characteristics for Vg=1V, calculated with drift diffusion (DD) and energy balance (EB) models under isothermal conditions. The remarkable shift of breakdown voltage is due to the well known over-estimation of the impact ionization rate by the DD model. Therefore, all further calculations and comparisons were performed for the isothermal energy balance (EB) and NEB models. For the NEB simulation the heat flux was set equal to zero at boundaries, except at the bottom of the device where a thermal resistor Rth =3.3 10 Kcm /W was connected to a 300 K source.



Figure 1. Drain current as a function of
drain voltage. DD and EB models.



Figure 2 shows the Id-Vd characteristics as predicted by the EB and NEB models for gate voltages held at 1, 2, and 3V respectively. Figure 3 shows the maximum lattice temperature in the device versus drain voltage. These results show significant self-heating in the breakdown mode, especially for higher gate voltages, and a noticeable increase in the breakdown voltage predicted by the NEB. The breakdown voltage increases due to the decreased impact ionization rate for elevated lattice temperatures.


Figure 2. Drain current as a function of drain voltage.
EB and NEB models. Vg=1, 2, and 3V.


Figure 3. Maximum lattice temperature as a function
of drain voltage. Vg=1, 2 and 3V.



The Id-Vd characteristics in the strong breakdown mode for Vg=2V are presented in Figure 4. The predicted behavior in the high current region is very different for the EB and NEB models. Compared with the EB model, the NEB model does not exhibit the snapback around 9V due to the decreased impact ionization rate. On the other hand, the NEB model clearly displays the second breakdown around 16V, which can not be obtained by the EB model. The maximum lattice temperature in this snapback point is 1300K.


Figure 4. Drain current as a function of drain
voltage. EB and NEB models. Vg=2V.



SOI Example

The simulated ultra-thin non-LDD SOI device has gate oxide, body, and substrate oxide thicknesses of 0.012, 0.05, and 0.45 µm respectively. The channel length is 0.5 µm. The doping concentrations in the channel, and source and drain are constant and equal to 1.5 10 and 5 10cmrespectively. The lattice temperature is set equal to 300 K along the bottom of the device, and the normal component of the heat flux is set equal to zero on the other part of the boundary.

Figure 5 shows the predicted drain current as a function of drain voltage, for gate voltages of 1, 2 and 4V, calculated using the EB and NEB models. Figure 6 shows the maximum lattice temperature in the device, as a function of drain voltage for the same set of gate voltages calculated using the NEB model. No kink effect consistent with experimental data for ultra-thin SOI devices was observed. As could be seen from figures 5 and 6, the self-heating effects are more pronounced for SOI devices than in bulk devices, due to low heat conductivity of the oxide. The typical negative differential conductance is observed for Vg=4V.


Figure 5. Drain current as a function of drain
voltage. EB and NEB models. Vg=1, 2, and 4V.


Figure 6. Maximum lattice temperature as a
function of drain voltage. Vg-1, 2, and 4V.


A self-consistent non-isothermal energy balance model has been developed and incorporated into the general purpose 2D device simulator ATLAS/S-Pisces. The electrical characteristics of submicron LDD MOS and ultra-thin SOI devices have been investigated for the first time using this model, and the results have been systematically compared with the results predicted by simpler models. The calculated results clearly demonstrate the influence of coupled non-isothermal and non-local carrier heating effects on the device characteristics. They also provide insight into the magnitude and nature of the discrepancies associated with the use of less general models.

These two examples clearly demonstrate that both non-local transport and self-heating effects must be accounted for when designing deep submicron devices for future generations of VLSI.



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[2] R. Stratton,
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[3].B. Meinerzhagen and W.L. Engl,
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[5].B. Meinerzhagen, K.H. Bach, I. Bork, and W. Engl,
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NUPAD IV Abstracts, Seattle, USA, pp. 91-96, 1992.

[6]. Y. Apanovich, E. Lyumkis, B. Polsky, and P. Blakey,
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[7]. Y Apanovich, R. Cottle, E. Lyumkis, B. Polsky, A. Shur, and P. Blakey,
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Proc. of the Third Intern. Workshop on Comp. Electronics, Portland, USA, pp. 107-110, 1994.

[8].Y Apanovich, R. Cottle, E. Lyumkis, B. Polsky, A. Shur, and P. Blakey,
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