Mixed-Mode Simulation Using SmartSpice



SmartSpice can now be used to perform analog circuit simulation within a mixed-mode simulation environment using the SimMatrixTM co-simulation backplane from Precedence Inc. Mixed-mode simulation allows circuits containing analog and digital components, or circuits described at multiple levels of abstraction, to be simulated simultaneously. This is achieved by allowing the designer to simulate each component of the design using the tools most appropriate for the task. For instance, SmartSpice can be used to simulate critical components in the design with SPICE level precision, while a digital simulator such as Verilog-XLTM can simulate digital components at a gate or behavioral level.

There are many benefits to be gained from simulating a design within a mixed-mode environment rather than using traditional analog simulation tools.

Faster Simulation Simulation run-time is dramatically reduced, even for the simplest of circuits, with minimal impact on the accuracy of the simulation. This is achieved by using more efficient algorithms to simulate non-critical digital components of the design. In addition, advanced synchronization algorithms minimize the number of synchronizations required, thus allowing each simulator to operate with fewer interruptions.

Increased Productivity The productivity of the designer is increased by the use of higher levels of abstraction to describe digital components. Overall productivity gains result from the faster simulation times and the lowered demand on system resources.


Mixed-Mode Simulation Concepts

Mixed-mode simulation is based on the SimMatrix co-simulation backplane. SimMatrix provides a coupling between the Verilog design environment and a number of client simulators, including SmartSpice, TimeMillTM, and LsimTM. In order to facilitate co-simulation, SimMatrix provides user driven partitioning and netlisting services, in addition to automatic event transfer and synchronization, during simulation. Simulation of the design follows the process flow shown in Figure 1. As can be seen there are two distinct phases, partitioning and simulation, performed by the partitioner and run time control tools respectively. The designer provides the Verilog design files and SmartSpice netlists describing the analog portion of the design. The initialization files which are also provided by the designer are used to set options when partitioning and simulating. During the actual simulation, the designer can view waveforms using both SmartSpice and Verilog.



Figure 1. MixedMode simulation process flow. The partitioner divides the design for each client simulator and the run time control tool performs the actual simulation.


Design Partitioning

Due to the coupling of SimMatrix to Verilog, it is necessary for the designer to describe the overall design in a Verilog format. Analog modules or subcircuits within the design, which are to be simulated using SmartSpice, are flagged with a special directive and appear as empty Verilog modules. The details of these modules, in addition to standard SmartSpice statements and commands, are then described in SmartSpice netlist files.

Prior to mixed-mode simulation, it is necessary to partition the design into a number of netlists, one for each of the simulators being used. This partitioning is performed automatically by SimMatrix using the partitioner tool. Each partition contains all the hierarchical information for the design, in addition to interface devices which will communicate events across simulation boundaries during simulation.


Mixed-Mode Simulation

During simulation SimMatrix monitors events at simulation boundaries and dispatches them to the appropriate simulators. Signal conversion from the digital-to-analog domain, and visa versa, is performed in SimMatrix and transmitted to and from SmartSpice by Norton interface devices at the simulation boundaries. These devices define switching thresholds for the translation of analog voltages to logic states during analog-to-digital conversion. For digital-to-analog conversion, the Norton devices convert logic states to voltages over a specified time thus ensuring the continuity of analog signals.

The synchronization of SmartSpice and Verilog by SimMatrix can be achieved using a number of different algorithms. The basic algorithm provided is commonly referred to as the lock-step method. This algorithm forces synchronization at each time-step within SmartSpice. This method ensures that synchronization is always achieved since both simulators operate concurrently. The disadvantage with this algorithm is that the latency of digital simulation is not exploited and simulation speed approaches that of a pure SPICE simulation.

The second synchronization algorithm is known as the optimistic look ahead method. This algorithm is far faster and much more efficient as synchronization is only performed when data needs to be exchanged between the simulators. Using this method, it is possible that SmartSpice will get ahead of digital events at the simulation boundary in which case reevaluation of the analog system will occur at the synchronization time point.


Bipolar ADC Example

The classic benchmark circuits for mixed-mode simulation are A-D and D-A converters. The example described here is a 12-bit successive approximation bipolar analog-to-digital converter (ADC). A schematic representation of the design of the ADC is shown in Figure 2. The shaded areas (SAR and DLATCH) are simulated in the digital domain using Verilog while the remainder of the design is simulated using SmartSpice. The analog input voltage, Vin, is to be converted to a 12-bit digital value. After conversion has finished, the output of the SAR (B11-B0) with B11 being the most significant bit, will represent this value.



Figure 2. Circuit schematic of a successive approximation bipolar ADC.



Due to the fact that the analog portion of the circuit is completely bipolar, it is necessary to change the conversion values when communicating signal changes between the two simulation domains using Norton devices.

These conversion values are by default set to standard TTL type values. High and low states are converted to 0V and -0.45V respectively in the analog domain, while the switching thresholds for logic high and low values are set to -0.35V and -0.36V respectively.

At the start of conversion, the output of the SAR will be set to half of its maximum 12-bit value of 8192. The comparator will compare the output voltage of the DAC (Vout) with Vin. If Vout is greater than Vin then the output of the SAR will be decreased, otherwise it will be increased. This will continue for 12 clock cycles, at the end of which Vout will be within 1LSB of Vin.

The results of simulating this design with an input voltage of 1V are shown in Figure 3 and Figure 4. Figure 3 contains analog waveforms generated by SmartSpice. The upper waveform is a plot of the output voltage of the DAC with respect to time. The conversion process is clearly shown and as can be seen Vout is approximately equal to Vin(1V) after 12 clock cycles. The lower waveform is the output of the comparator (Vcomp). If Vcomp is high then Vout is greater than Vin and Vout will be decreased at the next clock cycle.



Figure 3. The upper plot displays the variation of the output voltage
of the DAC with respect to time. The ouput comparator,
which is in fact an interface node, is displayed in the lower plot.



Figure 4. Waveforms observed in the digital portion of the design.

Figure 4 displays waveforms observed in the digital component of the design. DATA is an inverted version of the analog voltage Vcomp. The outputs of the SAR (B11-B0) are also shown. As can be seen the initial output of the SAR is 011111111111. Over the 12 clock cycles, these outputs change, with the final output of the SAR being 011100001000, which is the output of the ADC for an input voltage of 1V.



Mixed-mode simulation is essential when simulating circuits containing digital and analog sections, regardless of their complexity. SmartSpice, in association with SimMatrix and Verilog-XL, provides an effective solution to the problems inherent in typical mixed-mode simulation environments.



Silvaco would like to thank Marco Zelada of Microchip Technology Inc. for his helpful contribution.

SimMatrix and Precedence are trademarks of Precedence Inc., Verilog and Verilog-XL are registered trademarks of Cadence Design Systems, Inc., Lsim is a trademark of Mentor Graphics, and TimeMill is a trademark of Epic Design Technology, Inc.