ATHENA: The Complete Process Simulation Environment

ATHENA is a process simulation environment that meets the needs of modern simulation-driven technology development. Its design incorporates two key elements. The first is that it is able to simulate the complete range of processing steps. These include bulk processes, such as implantation, diffusion, and oxidation, for both silicon and compound semiconductor technologies; topography processes, such as deposition, etch, and reflow; and lithography processes, such as imaging, exposure, and development. The second is that users can supply a complete process flow and a mask layout as input and can then identify individual structures to be simulated as points, cut lines or regions on the layout.

This article highlights new features that have been incorporated in ATHENA during 1994. Applications-oriented examples are used to illustrate some of the unique capabilities of ATHENA.

The Architecture Of ATHENA

ATHENA is structured in a modular way around a set of tools that form a development "toolkit". The architecture of ATHENA is indicated in Figure 1. The four principal products are SSuprem4, Flash, Optolith and Elite. SSuprem4 simulates diffusion, oxidation and ion implantation associated with silicon technologies, and Flash simulates these processes for III-V technologies. Optolith simulates lithography-oriented processing steps such as imaging, exposure, and development [1]. Elite provides physically-based models for simulating topography-oriented steps such as deposition, etch and reflow. The Monte Carlo deposition option works in conjunction with Elite and the Silicide option works in conjunction with SSuprem4. The Monte Carlo implant option works with either SSuprem4 or Flash.

Figure 1. The modular architecture of ATHENA.

This flexible architecture provides many advantages. Different configurations meet the needs of all users, including the developers of unit processes, process integration engineers, production and manufacturing engineers, and industrial and academic researchers. These needs are met not only for silicon technologists but also for developers of III-V technologies.


Figure 2 demonstrates the power of the general input capabilities. It is a layout on which a cross section is selected, together with the corresponding mask polarities through the cross section. This patterning information was then used in conjunction with a complete process flow to create the structure shown in Figure 3.

Figure 2. ATHENA is tightly interfaced to the MaskViews layout editor.


Figure 3. Complete processing of complex structures is
facilitated by the layout interface with MaskViews. Here a
CMOS process flow is used to simulate NMOS and PMOS devices.


New Features In ATHENA Version 3.0

Adaptive Meshing

Fully automatic mesh adaptation is implemented. This capability eliminates the need for user intervention during gridding. Special attention has been paid to improve handling around material interfaces. Figure 4 shows a bipolar transistor structure for which the mesh has automatically adapted around junctions yielding good resolution.


Figure 4. This bipolar transistor example shows how the
adaptive meshing capability of ATHENA automatically
places mesh points in critical regions such as junctions.


Chemical Mechanical Polish Models

Two new models for chemical mechanical polishing (CMP) are implemented in Elite. They are the Burke model (hard polish) and the Warnock model (soft polish)[4,5]. The Burke model polishes the structure at a rate proportional to the pattern factor of the structure. The Warnock model calculates the polish rates based on calculated pad deformation and shadowing effects. Users can specify an isotropical rate component for use with either CMP model. The two polish models can be used together or separately.

Additional Compound Materials

Additional compound materials AlGaAs, InGaAs, SiGe, and InP are now available. Graded heterostructures can now be simulated, which means that it is now possible to simulate the fabrication of devices such as HBT's and HEMT's. Carbon is available as a dopant for GaAs.

C-Interpreter Interface

The ATHENA C-Interpreter interface allows the user to modify or define models for physical phenomena such as impurity diffusion, impurity segregation, or impurity activation. The ability to prototype new models conveniently, without accessing the ATHENA source code, is invaluable in industrial and academic research and development environments. Figure 5 shows the use of the C-Interpreter to model the activation of silicon implanted into GaAs material.


Figure 5. The C-Interpreter allows the prototyping of the new
models for processes that are not well understood
Here the C-interpreter is used to implement a new model
of the transient activation of a very high dose implant.


Monte Carlo Implant Secondary Recoil

Secondary recoil is implemented in the Monte Carlo implantation model. The model calculates the trajectory of secondary ions generated by the collision between the implanted ion and lattice atoms and allows complete amorphization dynamics to be simulated.

Impurity Activation Calculation

Active impurities as well as chemical impurities are now both available. Donor and acceptor concentrations are calculated from the active impurity concentrations.


The Fabrication Of A SiGe MOSFET

Figure 6 shows the results of process simulation of a Si-SiGe MOSFET [2]. The fabrication of the structure involves the use of conventional LOCOS processing, as well as the incorporation of silicon germanium material. The ability to handle each of these situations is unique to the latest version of ATHENA. The metalization that forms the contacts is deposited into via openings that were created using Elite to simulate wet chemical etching and dry reactive ion etching in order to produce the desired contact shape.


Figure 6. Flash allows process simulation of heterojunction
technologies Here this capability is applied to the
fabrication of a SiGe MOSFET.

Interconnect Metalization

Figure 7 shows the result of the process simulation portion of a calculation of the capacitances between conductors in a realistic multi-level interconnect structure. The overall calculation has three parts: first, the formation of a 2D multi-level interconnect structure using ATHENA; next, the conversion of the 2D structure to a 3D structure using DevEdit3D; and finally, the extraction of the interconnect capacitances using ATLAS/Interconnect3D.


Figure 7. 3D interconnect structures can be created from
2D ATHENA structures and analyzed by ATLAS. Here a
set of interconnect lines is shown with oxide intermetal dielectric
made transparent for easy visualization.


ATHENA was used to create a structure from two metal layers, one poly layer and dielectrics. The final 3D structure is a cross-over of Metal2 running in the x-direction. This crosses three Metal1 tracks running in the z-direction. Two additional poly tracks also run in the z-direction. Figure 7 shows the resulting structure.

Silicide Modeling

Figure 8 shows a 1D cross section through a silicide material system. The silicide capabilities of ATHENA have been in use for almost two years and are the most complete capabilities of this kind[3]. The figure illustrates the calculation of silicon as a diffusing species moving through the silicide layer. This calculation allows inclusion of both diffusion and reaction limited terms in determining the growth rate. The figure also shows arsenic redistribution that takes place as a result of material consumption and segregation phenomenon.


Figure 8. This figure shows the diffusion of silicon from the substrate
towards the silicides material. The inclusion of both silicon and
metal species as reaction and diffusion components makes for a
complete, physical calculation that can be applied to many siliciding materials.



ATHENA simulates a broad range of processing steps that can be performed in any sequence. It is able to simulate complete process flows in conjunction with layout information. This is necessary for the full exploitation of modern, simulation-driven development methodologies.



  1. T. Crandle, S. Leon, "Solving Optical Lithography Problems by Using Simulation", Solid State Technology, August 1994.
  2. S.P. Voinigescu, C.A.T. Salama, J.P. Noel, and T.I. Kamins, "Si/SiGe Heterostructure p-MOSFET with Triangular Ge Channel Profiles", ESSDERC Proceedings, 1994, pp. 143-146.
  3. T. Crandle, C.M. Li, M. Temkin, and P. Hopper, "A Two-Dimensional Model for Silicide Growth", VPAD, 1993.
  4. P. Burke, "Semi-Empirical Modeling of SiO2 Chemical-Mechanical Polishing Planarization", VMIC Conference, 1991.
  5. J. Warnock, "A Two-Dimensional Process Model for Chemimechanical Polish Planarization", Jour. Electrochem. Soc., Vol. 138, No. 8, Aug 1991.