A Modern Approach To 0.35 µm Technology Optimization

Dr. G. Le Carval (LETI, France) and P. Hopper (Silvaco)


Traditional experimental procedures for the development of new technologies have become very costly and time consuming. This has become especially apparent during the development of deep submicron technologies. The increased complexity of these technologies requires designers to deal with numerous structural and electrical parameters that interact in a nonlinear manner. In addition, the escalating cost of modern fabs makes experiments more expensive; and time-to-market considerations are providing a powerful impetus for accelerated development cycles.

The microelectronics industry is responding to these circumstances in various ways. Experimentation has been made more efficient, via the use of techniques such as Design of Experiments (DOE) and Response Surface Methodology (RSM). Simulation is being used more extensively to assist the development process. Simulation has typically been used in a rather unstructured way. The result has been simulation-influenced development. The latest trend is to combine the use of DOE, RSM, and calibrated simulation in simulation-driven development methodologies. Silvaco's Virtual Wafer Fab supports this trend.

Due to proprietary considerations there has so far been little sharing of the experiences that have been acquired with simulation-driven methodologies. This article presents an informative example of its use. The technology development that is described was all performed at LETI in Grenoble, France, as part of the GRESSI association with CNET.


Figure 1. An example of a response surface generated within the
Virtual Wafer Fab. This response surface shows how the VT adjust implant
dose and gate oxide growth time affect the trade-off between the threshold
voltages of n- and p- channel transistors.


Technical Background

PMOS transistors are often the performance limiting factors for deep submicron CMOS and BiCMOS technologies, and any increase that can be achieved in the saturated drain current of these devices will normally lead to improved circuit performance. However, increased drain currents must be achieved within the constraints imposed by other considerations such as the required threshold voltage and the maximum allowable leakage currents.

This article describes the optimization of a 0.35 µm PMOS transistor structure. The starting point is a previously developed device that has an N-Poly gate and exploits sophisticated channel and drain engineering. The fabrication of this device uses five implantation steps: three for channel formation; one for an LDD implant; and a tilted Halo implant for improved punch-through immunity. The goal of this work was to optimize the parameters associated with the five ion implantation steps.



Process and device simulators must be calibrated prior to performing simulation-driven optimization. he Virtual Wafer Fab simplifies the task of adjusting parameters to obtain "best fits" between measured

and simulated data. The calibration of ATHENA and ATLAS was performed using experimental data acquired during the development of the initial structure. If this data had not been available a previous calibration performed for a 0.5µm technology could have been used instead.


Optimization Methodology

A typical sequence of activities associated with simulation-driven optimization is as follows:

1. The optimization targets are specified.
2. A preliminary set of input variables is defined.
3. Parameter screening is performed.
4. A reduced set of input variables is defined.
5. An optimization strategy is established.
6. Simulated experiments are performed.
7. A model of the simulation data is generated.
8. Optimization is performed using the modeled data.
9. Experimental confirmation is obtained.

Optimization seldom proceeds linearly from step 1 through to step 9 and then ends. There is usually more than one complete loop, and there may be many additional iterations around subloops.


Device Optimization

The optimization of the 0.35¨µm PMOS transistor proceeded as follows.


Step 1: The Specification Of Targets

Three output parameters are of primary interest. These are: Idsat, the saturated drain current for Lg= 0.4µm, and Vg= Vd= 3.3V ; Ileak, the leakage current for Lg=0.3µm, Vg= 0 V and Vd= 3.3 V; and Vt, the threshold voltage, which is required by noise margin considerations to have a value close around 0.9V. The values of Lg correspond to worst-case values for a variability of +/- 0.05 µm in gate length.

An objective function was defined using Idsat and Ileak. This function gave primary weighting to the maximization of Idsat, and somewhat lesser weighting to the minimization of Ileak. The constraint that Ileak must remain below 10 pA/µm was introduced as a hard constraint.


Step 2: The Preliminary Input Variables

A total of eleven input parameters (five energies, five doses, and the tilt angle of the Halo implant) was included in the preliminary set of input variables. Each input variable was assigned a nominal (starting) value, as determined for the previously developed structure, and an allowable range. These ranges are indicated in Table 1.


Table 1. The ranges of the input parameters, and their relative influence on each
response. Doses are given in units of cm, energies in keV, and in degrees.


Step 3: Screening

The sensitivities of Idsat and Ileak to variations around the nominal values of the preliminary input variables were calculated. This was done using sensitivity analysis, which can be performed automatically within the Virtual Wafer Fab. The results of this screening are indicated in Table I. The qualitative importance of each input variable is given by the number of stars in the corresponding column, ranging from three stars (a major impact) to zero stars (virtually no impact).


Step 4: The Reduced Set of Output Variables

Two of the eleven input variables (the energy of the second channel implant and the energy of the LDD implant) were dropped because of their lack of impact on either Idsat or Ileak. This left nine input variables to be included in the optimization.


Step 5: The Optimization Strategy

The generation and visualization of multi-parameter models is complicated when the number of input variables exceeds four or five. It can then be a good idea to decompose the optimization into a sequence of smaller optimization problems. The sequence of problems can be solved iteratively until overall convergence to an optimum point is (hopefully) achieved. The chances of convergence are enhanced if the most important variables are isolated in one block that is processed first.

A two-step strategy was used in the present work. The nine input variables were partitioned into two blocks. The primary block contained all four parameters that impact Ileak, and included the three parameters that have the most impact on Idsat. The secondary block contained the other five parameters.


Step 6: Simulated Experiments

Simulated experiments were performed to generate the data required for the optimization procedure described above. The simulated experiments required for the primary block optimization were generated using a central circumscribed composite (CCC) design. Models for Idsat, Ileak and Vt were developed (see the next section), and were used to optimize the values of variables in the first block. Simulated experiments involving the variables in the second block were then run, and an optimization of the variables in the second block was performed. Some simple checks indicated that there was no need to perform additional iteration. A total of only 68 simulated experiments was needed to generate all of the data required for this optimization!


Figure 2. Simulated experiments can be defined in the
Virtual Wafer Fab using a popup window.


Step 7: Modeling The Data

The results of the simulated experiments were used to develop second order polynomial models for Idsat and log Ileak. The fit provided by these models was checked using regression analysis, and found to be excellent. Similar models were developed for the other parameters following the second set of simulated experiments. The fits were again excellent.

The Virtual Wafer Fab also supports neural net modeling. Neural net models can yield significant improvements in accuracy, and the improvement in accuracy often justifies the additional time that is required for training.


Step 8: Optimizing The Device

Optimization was performed using the second order polynomial models, and was therefore very efficient. The results obtained for the optimized doses are shown in Table 2. The original values are also shown, as are the electrical characteristics of both structures. An improvement in Idsat of more than 20 % is achieved with negligible degradation of the other parameters.


Table 2. The implant doses and electrical characteristics obtained
by the original approach and using simulation-driven optimization.


The simulation-driven methodology automatically provides information relating to manufacturability. Differentiation of the polynomial models yields the predicted sensitivities of electrical parameters to process variations. In the present case the process sensitivity calculation revealed no degradation in manufacturability.


Step 9: Experimental Confirmation

The final step in each optimization loop is experimental confirmation. A significant improvement in performance is usually obtained providing the initial calibration was done carefully. A judgement must then be made concerning the need for another pass through the optimization cycle. When multiple optimization cycles are performed the experimental results that are obtained at the end of each cycle can be fed back to improve the quality of the underlying calibration.


Convenience and Cost-Effectiveness

The Virtual Wafer Fab contains tools that substantially automate calibration, screening, the definition, generation, and execution of simulated experiments, modeling simulated data, and performing optimizations. This makes it convenient to use simulation-driven development. The total cpu time required for this study was several hundred hours, and the elapsed time in a networked computing environment was significantly less. Model generation and device optimization required additional hours of engineering time. Overall, a relatively small incremental expenditure of resources can result in significantly improved device and circuit performance.



Simulator-driven development methodologies can provide companies with a significant competitive advantage over those companies that still use earlier development methodologies. The Virtual Wafer Fab makes it more convenient to use simulation-driven development.



Portions of the work described here were contained in a paper presented at the 1994 European Solid State Device Research Conference (ESSDERC). We thank the other authors of that paper[1] for their significant contributions.



1. G. Le Carval, D. Poncet, G. Guegan, J.-P. Caire,
Proceedings Of The 24th European Solid State Device Research Conference,
Editions Frontieres, France, pp. 841-844, 1994.