Submicron Si/SiGe CMOS Circuit Potential Determined Using Mixed-Mode Device-Circuit Simulation


S. Voinigescu*, P. Rabkin+, C.A.T. Salama*, A. Tcherniaev+, R. Cottle+, and P. Blakey+
* Department of Elec. & Comp. Engineering, University of Toronto,+Silvaco International


High-performance, low-voltage, deep-submicron Si-based technologies are expected to provide the basis for future generations of digital VLSI circuits. The use of SiGe heterojunction devices in Si-based technologies appears very promising in this regard[1]. Blaze and MixedMode were used to establish the improvements in circuit performance achievable using a Si/SiGe CMOS technology in which the n-channel device is conventional, and the p-channel device is a Si/SiGe heterostructure MOSFET. This combination offers improved performance, due to the higher mobility of holes in SiGe; and greater resistance to hot-carrier aging, due to the high valence band potential barrier limiting hot hole injection in the cap Si layer and gate oxide [1].

The work described here is believed to represent the first time that a circuit containing heterojunction structures has been analyzed using mixed-mode simulation (i.e. physically-based numerical device simulation with conventional circuit simulation [2,3]). Mixed-mode simulation was needed to overcome the lack of a suitable compact circuit model for describing the parasitic conduction in the Si cap layer of a Si/SiGe MOSFET.



It is highly desirable to validate the simulator implementation and material parameters employed before using physically-based simulation in a predictive mode. The numerical model and the SiGe material parameters used in this work were validated by obtaining good agreement between calculated and measured transconductance characteristics of a recently reported Si/SiGe p-MOSFET [4] that has a uniform 20% Ge channel and a channel length of 0.25µm (Figure 1).


Figure 1, Comparison of simulated and experimental
gm-Vgs characteristics of a Si/SiGe p-MOSFET
with 0.25µm effective channel length.


The circuit performance of deep submicrometer Si/SiGe inverters was then calculated, and compared with calculated results predicted for Si CMOS inverters of identical linewidth. The Si/SiGe CMOS inverter consists of a conventional Si n-MOSFET and a Si/SiGe heterostructure p- MOSFET. The heterostructure p-MOSFET has a fully graded channel with the Ge mole fraction varying from 0 at the bottom, to 0.5 at the top of the structure (Figures 2 and 3). Such devices have been shown to exhibit higher transconductances and cutoff frequencies than devices with uniform SiGe channels [1], and are readily integrated in a VLSI CMOS process. For both the Si/SiGe and the Si inverters, the size of the p-FET is 10µm by 0.25µm (0.125 µm channel length) and that of the n-FET is 8µm by 0.25µm (0.125µm channel length). The devices were scaled according to the saturation velocities of holes and electrons in Si, and the output characteristics of the Si/SiGe p-FET and the Si n-FET are fairly well matched.


Figure 2. Layer structure of graded channel


Figure 3. Energy band diagram. Vertical section
under the gate Zero bias condition.


The transfer characteristics (Figure 4) and transient responses to an input voltage pulse (Figures 5 and 6) were simulated for both the Si and the Si/SiGe inverters. Inverter delay was monitored with respect to load capacitance (Figure 5) and bias supply (Figure 6). Despite using identical n-FETs, the Si/SiGe inverter is at least 40% faster than the Si inverter. This performance edge, which increases for larger loads and lower bias supply voltages, is attributable to the superior characteristics of the Si/SiGe p-FET in the linear region.


Figure 4. Si and Si/SiGe CMOS inverter transfer
characteristics. Output voltage V[3] versus
input voltage V]1].


Figure 5. Si and Si/SiGe CMOS inverter transients
for different load capacitances C. The input
voltage V[1] and the output voltage V[3] versus time.


Figure 6. Si and Si/SiGe inverter transients for
different supply voltages Vdd. Input V[1] and
output V[3] voltages versus time.


Further evidence of the superior circuit performance of Si/SiGe CMOS technology is given by results calculated for a 3 stage ring oscillator (Figures 7 and 8). The calculated delay per stage for a supply voltage of 2.5 V is 33 ps and 50 ps for the Si/SiGe CMOS and for the Si CMOS circuits, respectively. These values compare favorably with experimental Si SOI ring oscillator results, even though the simulated structures have larger substrate capacitances and do not employ LDD regions [5].


Figure 7. Si/SiGe 3 stage ring oscillator characteristics.
Output voltages V[1], V[2], and V[3] (for the first, second,
and third inverters respectively) versus time.


Figure 8. Si/SiGe and Si ring oscillator waveforms.
Output voltage versus time.



MixedMode is best suited for applications in which relatively few critical devices are simulated using physically based numerical models, and the rest are handled by compact models. The calculated delay per stage may be slightly underestimated as a result of simulating a ring oscillator with only three inverters. Practical ring oscillators use at least five, and typically more, inverters. Additional simulations of ring oscillators with more inverters will answer quantitatively the question as to what degree the delay per stage may be underestimated in the three stage circuit.



Carefully validated mixed-mode simulation has been used to investigate the performance potential of a deep submicron Si/SiGe CMOS technology. The results indicate a speed enhancement of 40% or more compared to a Si-only technology.



[1.] S.P. Voinigescu, P.B. Rabkin, C.A.T. Salama, and P.A. Blakey, "2D Numerical Investigation of Gate Structure, Band Alignment and Delta-Doping Effects on the Transconductance and Cutoff Frequency of Submicron Si/SiGe FET's", Proceedings of the 23rd ESSDERC, pp. 361-364, Grenoble, France, September 1993.

[2.] ATLAS II User Manual, Silvaco Data Systems Inc., Santa Clara, CA, July 1993.

[3.] A. Tchernaiev, R. Cottle, B. Freydin, E. Lyumkis, B. Polsky, and P. Blakey, "Efficient, Versatile and Robust Mixed Circuit-Device Simulation", NASECODE IX Abstracts, Copper Mountain, Colorado, USA, April 1993, pp. 107-108.

[4.] V.P. Kesan et al., "High Performance 0.25µm p-MOSFET's with Silicon-Germanium Channels for 300K and 77K Operation", IEDM, p. 25-28, 1991.

[5.] S. Parke, F. Assaderaghi, J. Chen, J. King, C. Hu, and P.K. Ko, "A Versatile SOI BiCMOS Technology with Complementary Lateral BJT's", IEDM, pp. 17.3.1-17.3.4, 1992.