Application Notes
Custom IC CAD
- 2-022 - Hipex RC: Accuracy Improvement in Parasitic Capacitance Extraction
- 2-021 - Hipex-RC: Virtual Connect Names for Unfinished Nets
- 2-020 - Expert: Calibre RVE Interface for DRC/LVS
- 2-019 - Hipex-RC: 7 Techniques for Reducing a RC Netlist
- 2-018 - Layout Verification in Batch Mode
- 2-017 - Efficient Bus Wiring in Expert
- 2-016 - Tips to Make PCells Using Javascript
- 2-015 - New Features Facilitate DRC Clean Layout and Parasitic Effect Debugging
- 2-014 - How to Modify MOSFET PCells for Expert’s Device Link
- 2-013 - Enabling Netlist Driven Layout with Standard Cells
- 2-012 - New Enhanced Possibilities of Netlist Comparison in Guardian LVS
- 2-011 - Using DRC Error Database to Analyze LVL Run Results
- 2-010 - Parasitic Back Annotation for Post Layout Simulation
- 2-009 - Creating LISA Scripts to Automate Layout Operations in Expert
- 2-008 - Customizing Expert with New Functions Using LISA
- 2-007 - Preserving Parametrized Cells When Translating Competitors’ Layout Database into Expert
- 2-006 - Central Hipex Database and Improved Hipex-C and Hipex-R Technology Files
- 2-005 - Selective RC-extraction Methods in Guardian LPE for Post-layout Circuit Simulations
- 2-004 - A Suggested Approach for Layout Versus Schematic (LVS) Comparison Using Guardian LVS
- 2-003 - Logic Gate recognition in Guardian LVS
- 2-002 - Well Proximity and STI Stress Effect Parameters Extraction in Guardian LPE
- 2-001 - Multi-Core Guardian DRC Benchmark Results