Jivaro

Netlist Reduction Platform

Jivaro™ is an extracted netlist reduction platform. It speeds up the simulation time, increases accuracy compared to reduction done by circuit simulators and also reduces memory footprint. It is integrated into all major design flows and several graphical user interfaces.

Introduction

Simulation of an extracted netlist with heavy parasitics can take a very long time. Jivaro’s netlist reduction makes simulation faster without the loss of accuracy. Netlist reduction is not simply data crunching or filtering because of accuracy requirements, stability, passivity, reliability and verifiability.

Features

  • Jivaro provides unparalleled netlist reduction capabilities for all types of parasitic netlist components: R, RC, RCC, RLC, RLCK, voltage or current controlled sources, substrate, package
  • Selective reduction: Reduction can be applied differently on selected nets or sub-circuits within the hierarchy
  • Parameterized reduction: Reduction can be applied with additional structure preserving requirements (For example: EM)
  • Jivaro works for all design styles like RF, Analog, Mixed-signal, Digital, Memory etc.
  • Jivaro is process node independent; it can be applied to any process
  • Jivaro is used in production with backend flows from all major EDA vendors

Benefits

  • Acceleration of all simulation suffering from parasitics
  • Reduction of the simulation time with the same degree of accuracy
  • Reduction of the simulator’s memory footprint
  • Reduction of memory storage requirements of extracted netlists

Fig: 1 Reduction in runtime

Applications

  • Memory, Analog, Mixed-signal, RF, Timing

Technical Specifications

  • Major file formats supported: DSPF, SPEF, HSPICE, Spectre, SPICE3, CaliberView