Jivaro

Parasitic Reduction for Fast Simulation

Jivaro™ is an extracted netlist reduction platform. It speeds up the simulation time, increases accuracy compared to reduction done by circuit simulators and also reduces memory footprint. It is integrated into all major design flows and several graphical user interfaces.

Introduction

Jivaro™, a unique, stand-alone tool, is a solution dedicated to the reduction of parasitic networks. It speeds up post-layout simulation of huge parasitic extracted circuits, while keeping a very high accuracy.

Jivaro has been proven to dramatically accelerate IC simulation while preserving accuracy. It has been adopted by leading IDM and fabless companies worldwide. Jivaro can be used for designs at technology nodes down to 7nm.

Netlist Reduction Platform

Jivaro is integrated into all major design flows and several graphical user interfaces.

 
Jivaro Flow
Fig. 1: Jivaro is a reduction tool independent from the extractor and the simulator

Simulation of an extracted netlist with heavy parasitic takes a long time. Jivaro’s netlist reduction makes simulation faster without loss of accuracy.

   
Jivaro2 Jivaro2
Fig. 2: Jivaro allows to significantly reduce the impact of parasitics on SPICE and SPICE-like simulation time, while preserving their effects on the accuracy of the results.

Benefits

  • Reduced simulation time with no loss of accuracy
  • Reduction of the simulator’s memory footprint
  • Reduction of memory storage requirements of extracted netlists