Overview
Silvaco offers a complete portfolio of SIPware Foundation IP for the creation of ASICs and SoCs for almost any process node

  • Standard Cell Libraries for digital logic
  • I/Os, both general purpose and specialty, and ESD structures
  • Memory Compilers for SRAMs, ROMs, and register files

For over twenty years, the Nangate team, now a part of Silvaco, has been providing Foundation IP to the design community. Silvaco is committed to offering best-in-class components and a full set of services: a one-stop shop for chip developers and foundries.

Legacy Standard Cell Libraries
There are several established foundries for mature process nodes at 110nm and above. These mature processes have been in the market for over twenty years. The standard cell libraries that were developed earlier do not include recent technology developments. They can be improved for power footprint, performance, and area by employing:

  • Tapless architecture
  • Clock gating
  • Vt variants.
  • Power management kits (PMK) & multi-power islands
  • Multi-bit FFs
  • Fine grain sizing
  • Complex function matching

Silvaco SIPware Standard Cell Foundation IP
With 700 to 1,200 standard cells, multi VTs and track heights, the Silvaco standard library offers thousands of cell variants, enabling applications from ultra-low power to high speed. Silvaco carefully sizes each cell family in the library, optimizing transistor sizes, P/N ratios, and drive strength granularity for further power and performance gains.

Cello, Silvaco's EDA platform for layout optimization, enables a new level of optimization, with 35% area and 20% power reduction compared to off-the-shelf libraries from other vendors. Multi-bit and multi-height standard cells boost routing density even further by reducing pin count and packing more functionality inside standard cells. For example, the detailed review and exploration of 28nm design rules by Silvaco engineers resulted in the creation of an ultra-high density low-power library with a gate density of four million gates per square millimeter, the maximum possible for that node.

SIPware Foundation IP libraries support multiple foundries, multi-VT, and multi-bit FFs. They come with standard and custom PVT corners. For each library, add-ons include power management kits (PMKs) and ECO kits with fixed pattern for FEOL layers. Through the Cello platform, library creation, migration, and optimization services are available down to 7nm process nodes.  Off-the-shelf libraries targeted specifically to different foundries include:

  • 6/7/9/10/12 track libraries for the 180/152nm, 130/110nm, 90/80nm, and 65/55nm process nodes
  • 7/8/9/10/12 track libraries for the 40nm and 28/22nm nodes

To use a Silvaco SIPware Foundation library, contact Sales@silvaco.com or request it from your foundry.

I/O and ESD Protection Foundation IP

Silvaco has partnered with Certus Semiconductor for I/O and ESD cells and associated development services. Off-the-shelf I/Os from foundries or design IP provider provide basic performance without optimization for power, features or area. Modern interfaces are a complex mix of voltage domains, power modes, and must serve multiple purposes that challenge design teams. Certus provides optimization services for this complex mix of operating requirements, while keeping device area to a minimum. Certus optimizes the entire I/O system, including packaging, pad rings by tailoring the I/O, and ESD cells to cost and product needs. Multiple proven I/Os and ESD cells for various foundries are available off-the-shelf.

Our area of expertise includes the following:

  • RF ESD:  Low capacitance RF ESD solutions, tailored to a customer's specific design
  • Wired High-Speed Interfaces (HDMI, LVDS, USB, TIA’s, XAUI, and 28Gb SERDES):  Extreme ESD robustness and unique needs, such as 5V tolerance, fail safe, EOS, and  low capacitance for optimal signal integrity
  • Multi-Voltage Digital I/Os: GPIOs, fail safe GPIOs, and open-drain IOs (ODIO)
  • Multi-Protocol I/Os:  Single IO designs that can comply with multiple electrical standards, reducing PAD cell counts, simplifying product variants, and helping customers target broader application spaces with single designs
  • High Voltage Solutions: Unique techniques for 10V, 20V, and larger voltage structures on low voltage CMOS processes; optimize ESD in BCD processes
  • Rad-Hard/High-Temp:  Certus has experience developing custom I/O’s with rigorous temperature and radiation tolerance requirements
  • Custom IO: Optimized for power, area, modes, and features

On-chip Memory Foundation IP

Silvaco has partnered with Mobile Semiconductor for memory Foundation IP. We offer leading edge SRAM, ROM, and register file compilers optimized for applications requiring ultra-low power, low leakage, or ultra-high performance. Our low voltage SRAMs can operate at minimal voltages and have ultra-low power standby capabilities to extend effective battery life of end products.

Applications include:

  • Internet of Things (IoT) consumer and commercial products
  • Low power digital signal processing (DSP)
  • Low power networking applications using standards such as Bluetooth Low Energy (BLE)

We have over fifty memory compilers targeting processes ranging from 90nm down to 12nm.  At the 28nm node, there are sixteen different compilers, many of which were sponsored by GlobalFoundries.  Their low power technologies include:

  • Clock Gating: Reduces dynamic power of memory banks composed of multiple memories
  • Dual Voltage: Level shift between periphery and array supplies supports low voltage digital logic to reduce dynamic power. Supplies fully isolated for power off
  • Speed Grades: Select the optimum speed/leakage tradeoff enabling both high speed and low power retention mode
  • Optional Power Switches: Provide maximum flexibility for power down modes with easy integration including output isolation
  • Five possible power modes

For more information on Silvaco standard cell library Foundation IP, or I/O, ESD protection, and Memory Foundation IP,
contact Sales@silvaco.com.