Automatic slope and load Table Selections (ATS) for easy setup of config file

Cell Characterization and Modeling

AccuCell XT ™ automates the characterization and validation of libraries of standard cell, I/O and custom cells. It is tightly integrated with the SmartSpice circuit simulator for sign-off accuracy. AccuCell XT is well-suited for high performance, low power and timing-critical cell based design flows.


Characterizing cell libraries can be a labor intensive, manual process. Many steps are involved to accurately identify functions, define cell transitions, create vectors, run simulations and extract results to build – then verify – the models. Silvaco’s AccuCell XT replaces these labor-intensive steps with a highly automated flow, reducing weeks-long tasks down to days. 

Important to AccuCell XT’s automation is its automatic function extraction and smart vector generation that produces optimized vectors for characterization, with no redundancies, depending upon the specific cell characterization needs. This includes delays, output slews, input and maximum capacitance, setup and hold, power. etc. It supports complex cells, differential logic and cells with multiple inputs/outputs. AccuCell XT automatically generates the table selection and no intermediate steps are needed for automatic model generation. The outputs are typically the Liberty .lib (including timing, power, leakage), Verilog and datasheets.

Typical uses of AccuCell XT include:

  • New library characterization
  • Re-characterize commercial libraries
  • Migrate to a new process or foundry
  • Characterize custom cell libraries
  • Characterize complex cells
  • QA of existing libraries


  • Generate accurate single-pass, state-dependent timing, power, leakage and noise LibertyTM .lib libraries for advanced technologies
  • AccuCell XT multi-thread performance scales approximately linearly with the number of CPUs used for characterization. No limit on the number of CPUs that can be used
  • Fast API based integration with SmartSpice
  • Characterization can be run in parallel on either multi-core machines or over a network by using Sun Grid Engine (SGE)
  • Powerful table-based user defined vector scripting option enable customization of unique characterization requirements
  • Supports the latest designs in both static and dynamic cells
  • Sample the minimum number of points of current waveform for accurate characterization in CCS modeling by filtering out the noise, spike and possible faked peak points from curve


 Automation and Ease of Use

  • Powerful scripting environment permits specification of a cell and simulator characterization and library creation options
  • Netlist screening option for valid input circuit traps and avoid timely errors
  • Automated setup from an existing .lib template for easy library re-characterization
  • Automated maximum capacitance and slope determination with or without variable slew or delay degradation
  • Automated state-based input pin capacitance measurement with multiple reporting options


Fast and Accurate

  • Concurrent timing and power characterization results in near zero overhead for power library generation
  • Linear speed up
  • Automatic vector sizing option for optimal SPICE characterization run times

Flexibility & Industry Standard Output

  • Flexible simulation bypass, debug and reporting options enable rapid validation of scripting solution and root cause analysis of characterization effects
  • Automatic generation of Mentor ATPG format test library
  • Support for user defined I-V, glitch, noise immunity and noise propagation options
  • Selectable and customizable Verilog modeling options for support of various simulator and regression / back-annotation verification methods
  • Automatic HTML cell library datasheet generation
  • Non Linear delay model (NLDM) and CCS timing driver and receiver modeling support
  • CCS power dynamic current (propagated and hidden), leakage current (P/G and gate), RC intrinsic parasitic modeling support
  • Flexible characterization and reporting options for optimal state-based leakage power, internal power (switching and hidden) and average power analysis in NLPM

QA and Validation Capabilities

  • Automatically generates Verilog testbench with vectors for function verification
  • Special audit mode options for advanced access to all run-time info for QA validations
  • Graphical .lib viewer for QA analysis and comparison of timing and power result details

 Advanced Capabilities

  • Advanced SOI and un-buffered input options
  • Supports advanced multi-point slope or active-driver input stimulus for accurate VDSM characterization
  • Support for active loads for accurate low voltage measurement and user defined passive and active non-linear loading effects
  • Advanced fast evaluation of setup & hold, recovery & removal and minimum pulse width characteristics with extension characterization options supports both static and dynamic storage circuits with level, edge and pulsed inputs with multiple clocks
  • Tri- state driver characterization supports both conductance and current measurement
  • State of the art strength and state based ordered binary decision diagram (OBDD) method automatically extracts cell functions and generates optimal vectors required for accurate SPICE characterization of the latest VDSM effects including simultaneous switching


  • Characterization of standard cell libraries including custom cells

Technical Specifications

  • 100% HSPICETM and SpectreTM compatibility for all public nodes
  • Inputs: SPICE netlist, Configuration files
  • Outputs:
    • Liberty (.lib) (Non-linear delay model (NLDM), Non-linear power model (NLPM), CCS timing and power)
    • Verilog
    • HTML
    • Vital
  • Supported SPICE simulators: SmartSpice, HSPICE, Spectre, Eldo