Dynamically links in the capabilities of the SmartSpice Circuit Simulator and the SILOS Verilog Simulator at run time

Mixed-Signal Simulator

Silvaco’s Harmony™ is an analog/digital mixed-signal simulation solution that delivers the industry’s highest performance and accuracy. It utilizes a single kernel simulation architecture generated by dynamically linking the SmartSpice analog circuit simulator and the Silos digital simulator at run time. It includes a powerful AMS viewer to create, debug and simulate any mixture of analog and digital circuits.


The growing analog content and increasingly complex interfaces in today’s SoC designs necessitates the exhaustive simulation of significant analog content together with digital logic portions of the design. In mixed-signal simulators, performance is typically bound by the execution speed of the analog blocks and the simulation technology used to combine the analog and digital partitions. Harmony’s superior performance is a result of leveraging the industry’s premier SPICE simulator, SmartSpice, the well-proven digital simulator Silos and a highly optimized simulation kernel built at run time.  

Designers select which parts of their circuits to optimize for accuracy (SPICE) and which parts for speed (Verilog). A single parser reads the design and testbench expressed in Verilog, SPICE, Verilog­-A and Verilog­-AMS. Harmony performs optimal simulation initialization, synchronization and convergence for both analog and digital portions of the design. The highly productive mixed-signal simulation environment includes mixed signal waveform viewer, hierarchy explorer and interactive source code editor.

Figure 1: Harmony Analog/Mixed-Signal Simulator with Integrated AMS Viewer


  • Verilog-A language supports top-down design via behavioral modeling and bottom-up verification
  • Language synchronization in connect modules for all analog to digital interfaces using Verilog-AMS 
  • Testbench of stimulus and response can be any combination of analog and digital signals using Verilog or SPICE syntax
  • Intuitive, interactive debugging environment to create, debug and simulate any mixture of analog (SPICE) and digital (Verilog) circuits
  • Multi­-window, customizable data analyzer controls pan and zoom, timing markers, using interactive “drag & drop” capture, and waveform display for signals and expressions
  • Real­-time access and analysis of all expressions, variables, modules, signals, vectors, and registers
  • Back-annotation of timing information available using SDF
  • SmartView offers complete post-processing tools for composite diagrams, histograms, vector calculator, FFT analysis and eye diagram plots


  • Industry leading speed, accuracy, and convergence due to single kernel simulation architecture leveraging SmartSpice and Silos engines
  • Offers largest capacity of any true SPICE circuit simulator- up to 8 million devices
  • Productive, easy-to-use and powerful environment for both novices and experts

Figure 2: Harmony Single Waveform Viewer


  • Support for SPICE models for traditional technologies (Bipolar, CMOS) and emerging technologies (e.g TFT, SOI, HBT, SiGe)
  • Mixed-Signal

Technical Specifications

  • Input supported: Verilog, HSPICE & Berkely netlist, Verilog-A, SPF/DSPF, SDF back annotation
  • Output supported: rawfiles, FSDB, VCD
  • Support for Verilog-AMS and Verilog-A, IEEE 1364-2001 for Verilog HDL and Programming Language Interface (PLI)
  • HSPICETM compatible for netlists, models and analysis