Berkeley Common-Multi-Gate Transistor Model

An Advanced Physical Compact Model for Nano-FETs

The Berkeley common-multi-gate (BSIMMG) model is developed to meet the present and future needs of circuit designers employing advanced nano field-effect transistors (nano-FETs), such as FinFETs, with a potential to extend the technology roadmap into sub-25nm region. The BSIMMG model provides maximum versatility regarding multi-gate device geometry, novel materials and fabrication technology without compromising the ease of use and simulation efficiency characteristic for the previous generations of BSIM compact models.

Model Features

  • Surface potential based model with extra electrostatic control from the end-gates
  • Optional simplified surface potential solution for further improvements of the computational efficiency
  • Quantum mechanical effects
  • Corner-induced effective width reduction
  • Short channel effects including threshold voltage roll-off, DIBL, sub-threshold slope effects and channel length modulation
  • Poly-silicon gate depletion effects
  • Mobility degradation
  • Hybrid-surface-orientation mobility
  • Velocity saturation
  • Velocity overshoot with source end velocity limit
  • The internal and external, bias dependent, series resistance model
  • Gate tunneling current
  • Gate induced drain and source leakage currents (GIDL, GISL)
  • Impact ionization
  • Non-quasi-static effects
  • Parasitic capacitances
  • Junction capacitances and currents
  • Temperature effects and self-heating
  • Thermal/flicker/shot noise
  • Geometry scaling and binning of the model parameters


Benefits of Using BSIMMG

  • Versatility in choosing double, triple, quadruple or cylindrical multi-gate FET structures realized either in bulk silicon or SOI technology
  • Based on physical surface potential formulations, the BSIMMG model is continuous, symmetric, scalable and predictive over wide range of device parameters
  • The BSIMMG model captures almost all the important physical phenomena specific for nano-FETs
  • Parameters for non-silicon channel devices and high-k metal-gate stack structures
  • Adjustable complexity of the extrinsic RC network and surface potential solution to the required model accuracy and simulation efficiency
  • Possibility to switch between the BSIM and PSP based channel mobility models.


Different multi-gate architectures in BSIMMG

The choice of SOI or silicon bulk multi-gate technologies in BSIMMG Surface potential in BSIMMG in comparison to 3-D simulation

Normalized capacitance from BSIMMG model (lines) and TCAD (symbols) The third derivative of the BSIMMG drain-source current in the Gummel symmetry test for different gate voltages

The transient response of the 17-stage ring oscillator test case .


Silvaco Implementation

  • The BSIMMG model is implemented in SmartSpice as BSIM-CMG Level=105 - Berkeley release June 2011 version 105.03
  • Silvaco’s implementation is fully compliant to the original Berkeley Verilog-A code for the BSIMMG model version 105.03.
  • The node collapsing scheme is selected by combination of the BSIMMG control parameters specified in model and instance device statements
  • Print, plot, save or measure the most important device internal variables during and after simulation
  • Silvaco’s implementation is compatible with VZERO and BYPASS options and parallel architecture algorithms to achieve greater speed performance as well as DCGMIN option for improved convergence


  1. M. V. Dunga, C.-H. Lin, M. Niknejad, and C. Hu, “BSIMMG: A Compact Model for Multi-Gate Transistors” in Planar Double-Gate Transistor, A. Amara, O. Rozeau, eds., Springer, 2009.
  2. M. V. Dunga, Ph.D. Dissertation: Nanoscale CMOS Modeling. UC Berkeley, 2007.
  3. B. Yu, H. Lu, M. Liu, and Y. Taur, “Explicit continuous models for double-gate and surrounding-gate Mosfets,” IEEE Transaction on Electron Devices, vol. 54, no. 10, pp. 2715–2722, October 2007.


Rev. 012014_04