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TCAD
Overview
Process Simulation
Device Simulation
Interactive Tools
Virtual Wafer Fab
PARASITIC EXTRACTION
Overview
RC Extractor for Realistic 3D Structures
Full Chip LPE Rule File Generator
3D RF Passive Device Modeling
SPICE Simulation
Overview
Parallel SPICE Simulator
Analog/Mixed-Signal Simulator
RF Circuit Simulator
Waveform Viewer
Verlilog-A Environment
Fast Circuit Simulator
SPICE MODEL EXTRACTION
Device Characterization and SPICE Modeling
Statistical Parameter and Yield Analysis
Device Modeling for New Technologies
LIBRARY/MEMORY CHARACTERIZATION
Cell Characterization and Modeling
Block Characterization, Modeling and STA
ANALOG/CUSTOM DESIGN
Overview
Schematic Editor
Layout Editor
DRC/LVS/NET Physical Verification
Full-Chip Parasitic Extraction
Extracted Netlist Analysis & Reduction
Overview
DIGITAL DESIGN
Overview
Verilog Simulator
Mixed-Level Fault Simulator
SPICE Netlist to Verilog Gates Converter
Verilog Netlist to SPICE Netlist Converter
Place and Route Design Flow
POWER INTEGRITY SIGNOFF
Power-EM/IR-Thermal
VARIATION-AWARE DESIGN
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PDKs
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Latest Baseline
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Digital Encryption Standard
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Xena IP Management
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