Since our beginning we have believed in the idea that "It's the System that is important".  A good system level design is crucial to designing a successful product.  This is certainly true for SOCs.  Our subsystems have been designed with the total system in mind.  That's why our subsystems are delivered with the infrastructure (bus systems), memory systems and peripherals all in a verification environment that emulates the software and hardware a system level. 

Our IP Subsystem environment is easily expanded to include your peripherals or special interfaces.  Our Verilog/SystemVerilog based verification environments make it easy to use with any of the standard simulation tools from Cadence, Mentor Graphics or Synopsys.  

All of our peripherals, DMAs, buses and memory controllers are delivered with comprehensive stand-alone tests using AMBA® standard transaction or Bus Functional Models (BFM).