The Data Encryption Standard (DES) IP Core is a complete implementation of the Data Encryption Standard (DES) documented in the U.S. Government publication FIPS 46-3.

The DES core is a block cipher, working on 64 bits of data at a time.  The DES core uses a single 64 bit key of which only 56 bits are used. Encoding and decoding operations are performed in 16 clocks per block, in Electronic Codebook (ECB), Cipher Block Chaining (CBC), and Output Feedback (OFB) mode.

The DES core is fully synchronous using only one clock signal and can be implemented in both FPGAs and ASICs.  The DES IP Core is delivered as Verilog RTL Source code.

This DES IP Core version is implemented to minimize the gate count and FPGA resources. The design does not use any memories such as SRAM.


  • FIPS 46-3 Standard Compliant
  • Encryption/Decryption performed in 17 cycles
  • ECB, CBC, OFB Modes
  • 56 bits of security
  • Small gate count
  • For use in FPGA or ASIC designs


  • Verilog Source
  • Complete Test Environment
  • AHB Bus Functional Model
  • C-Sample Code