The ColdFire V4 Core & Standard Product Platform (SPP) combines the ColdFire V4 Core with industry-proven platform peripherals to form a complete high-performance microcontroller subsystem supported by a vast ecosystem of development tools and runtime software. With the ColdFire V4 Core & SPP, you get:

  • Performance—over 500 DMIPS at 345 MHz
  • Reliability—from processor and peripheral IP already deployed in millions of embedded systems worldwide
  • Rapid time-to-market—in just a few hours you can be developing software on your own FPGA implementation of the ColdFire V4 Core & SPP


The ColdFire V4 Core is a high-performance implementation of the ColdFire architecture with 1.54 DMIPS/MHz instruction throughput and high-speed Harvard local buses with tightly-coupled instruction and data caches and local SRAM. The ColdFire V4 Core also features an MMU for full operating system support plus special arithmetic hardware including a divider and enhanced MAC (EMAC) for faster execution of DSP algorithms, and an FPU for single and double-precision floating-point calculations.

Like all ColdFire architecture processors, the ColdFire V4 Core features a variable-length instruction set for maximum code density, industry-standard AMBA 2 AHB system bus interface for rapid system integration, and a wide selection of development tools, operating systems, drivers, and libraries from both commercial and open source providers.


The ColdFire V4 Core & SPP is currently available in three different product configurations. The CFV4SPP version of the ColdFire V4 Core & SPP includes the ColdFire V4 Core and the fully-integrated peripherals shown in Figure 1, implementing functions commonly needed for embedded systems including Ethernet, interrupt control, DMA, timers, and various serial interfaces. An AMBA 2 AHB Crossbar Switch provides the system interconnect, supporting simultaneous AHB transfers between multiple masters and slaves. In addition to the on-platform AHB masters and slaves, the Crossbar Switch supports connection of external AHB masters and slaves.

The CFV4SPPC2 includes two Fast Ethernet Controllers for additional Ethernet connectivity, but is otherwise identical to the CFV4SPP. For systems that do not require Ethernet connectivity, the CFV4SPPC1 omits the Fast Ethernet Controller to reduce system gate count. Other variations of the V4 ColdFire Core & SPP with user-selected peripherals are available upon request.


Figure 1: Example SoC Using V4 ColdFire Core & SPP



On-board peripherals and their features include:

  • FlexBus Controller
    • Connects up to 6 on-chip or off-chip memories/devices
    • Independently programmable transfer characteristics for each device (wait states, address setup/hold)
  • Enhanced DMA (eDMA) Controller
    • 16 independently programmable DMA channels
    • Programmable channel arbitration modes
    • Support for channel linking and scatter/gather operation
  • Fast Ethernet Controller(s): one for CFV4SPP, zero for CFV4SPPC1, two for CFV4SPPC2
    • 10/100 Mpbs Ethernet support
    • Half and full-duplex modes
    • Media Independent Interface (MII) or 7-wire interface to Ethernet PHY
  • Interrupt Controller
    • 64 programmable interrupt sources, 7-33 of which are available for external interrupts depending on the number of Fast Ethernet Controllers included
    • Unique vector for each interrupt source
    • Support for low-power mode wake-up
  • Queued SPI (QSPI) module
    • Programmable queue for up to 16 SPI transfers
    • Four chip-select lines for up to 16 devices
    • Programmable baud rate, before-and-after transfer delays, clock phase and polarity
  • I2C interface module
    • Support for the original Philips I2C bus protocol
    • Support for baud rates up to 3.4 Mbps
  • 3 UARTS
    • Programmable clock source, data formats, and modes (normal/loopback)
    • Error detection
    • Four maskable interrupt conditions
  • 4 DMA Timer modules
    • Programmable clock source
    • Programmable prescaler
    • Programmable interrupt or DMA request upon timer event
  • Miscellaneous Control Module (MCM)
    • Software watchdog timer
    • Reset status, low-power mode control, and core fault status registers


The ColdFire V4 Core & SPP features software-controlled shutdown of selected clocks to support a variety of chip-level low-modes:

  • Independent shutdown of selected peripheral clocks
  • Shutdown of the ColdFire V4 Core CPU clock in response to a ColdFire STOP instruction; the ColdFire V4 Core local SRAM Controller clock may optionally be kept running in STOP mode to support access to local SRAM from external AHB masters


The ColdFire V4 Core & SPP supports ColdFire Debug Architecture Revision D+, including:

  • Background Debug Mode (BDM)
  • Real-Time Trace (RTT)
  • Real-Time Debug (RTD)
  • On-chip, 128-entry trace buffer for low-cost trace over BDM


The ColdFire architecture is supported by a vast assortment of development systems/tools and run-time software including libraries, stacks, drivers, and operating systems from providers such as Freescale, Green Hills Software, Wind River Systems,  CodeSourcery, and many more. For example, the Sourcery G++ tool suite from supports ColdFire V4 targets and can be used to develop new code or to retarget ColdFire V1/V2 programs to ColdFire V4 devices. A free version of the GNU compiler supporting ColdFire V4 targets is also available from

Freescale offers development boards, software, and CodeWarrior Development Tools (including a free version supporting the ColdFire V4 architecture). In addition, there are several operating systems supporting the ColdFire V4 architecture, including Linux/uClinux and several RTOS’s, such as the MQX RTOS from Embedded Access, Inc.


The ColdFire V4 Core & SPP gate count depends on the selected on-board peripherals, synthesis tool, and target technology. The gate count for the CFV4SPP shown in Figure 1 in a typical 90-nm technology is 396K gates. The maximum CPU frequency for the same target technology is approximately 345 MHz. Omitting the Fast Ethernet Controller (CFV4SPPC1) reduces the gate count to 370K gates.

The CFV4SPP achieves over 100 MHz in most FPGA devices and uses approximately 50,000 LUTs in an Altera Stratix III device. For a Stratix III EP3SL200F1152C2, that is less than 32% utilization.


  • Synthesizable Verilog source code
  • Integration testbench and tests
  • Documentation
  • Scripts for simulation and synthesis with support for commonly-used EDA tools

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