This is an implementation of an I2C Slave with a FIFO interface to the AMBA APB bus.  The I2C peripheral contains the following main sections:

  • Configuration Registers
  • Read and Write FIFOs
  • Interrupt Generator
  • I2C Engine

Configuration registers are written and read by the processor via an APB Interface. 

The I2C engine converts I2C read/write requests into FIFO writes/reads.  I2C writes usually occur with no delay; however, reads usually cause the engine to assert SCL low (stretch the clock) to gain time for the read request to be fulfilled by the processor through the APB.  An interrupt is generated to facilitate this.  If the processor keeps the FIFOs full, this overhead can be minimized.  Optionally, a flow control mode may be selected which stretches the clock for all reads and writes.  In this mode the processor must respond to an interrupt and clear the stretching.

FEATURES

  • AMBA® APB Compatible
  • Standard I2C - Inter-Integrated Circuit Bus Interface
  • I2C Slave Mode
  • I2C Transmit and Receive Engine
  • AMBA® APB Configuration Registers
  • Read and Write FIFOs
  • Interrupt Generation Logic

DELIVERABLES

  • Verilog Source
  • Complete Test Environment
  • APB Bus Functional Model
  • C-Sample Code