This is an implementation of a standard I2C Master.  The I2C peripheral contains the following main sections:

  • Configuration Registers
  • Clock Divider/Clock Select
  • Command FIFO and Read Data FIFO
  • I2C Transmit and Receive Engine
  • Interrupt Generation Logic

Configuration registers are written and read by the processor via an APB Interface.  The clock divider/clock select module is used to customize the frequency of the I2C portion of the module.  Two separate FIFOs are used – one for storing up to 32 commands from the APB Interface, the other for storing up to 16 bytes of read data from the I2C Bus.  The transmit engine reads commands from the command FIFO and implements these as I2C instructions.  The receive engine monitors the I2C bus for slave responses, and stores data in a Read Data FIFO, the contents of which are available to the processor on the APB Interface.  Various conditions can cause an interrupt to be generated.

FEATURES

  • AMBA® APB Compatible
  • Standard I2C - Inter-Integrated Circuit Bus Interface
  • I2C Master mode
  • I2C Transmit and Receive Engine
  • AMBA® APB Configuration Registers
  • Clock Divider/Clock Select
  • Command FIFO and Read Data FIFO
  • Interrupt Generation Logic

DELIVERABLES

  • Verilog Source
  • Complete Test Environment
  • AHB Bus Functional Model
  • C-Sample Code