The SDRAM Controller provides the interface between external SDRAM devices and an AHB system bus. This controller can control quad-bank SDRAM devices up to 256MB. The controller has several configuration options for compatibility with a wide variety of devices. Requests from the AHB bus are passed on to the control engine which handles device initialization, refresh, and read/write accesses to memory. Accesses to SDRAM always occur in bursts. Single accesses are not supported.  A FIFO is used to pass read/write instructions to the control engine and a read buffer is used to reduce read latency and improve performance.


  • Interfaces AHB bus to external SDRAM
  • AMBA® AHB Compatible
  • Supports 8bit, 16bit and 32bit external modes
  • Supports byte (8bit), halfword (16bit) and word (32bit) internal accesses
  • Supports Burst mode
  • Supports SDR only


  • Verilog Source
  • Complete Test Environment
  • AHB Bus Functional Model