What's New in the Latest Baseline Release
The baseline release is available for download. The release notes linked below contain the latest changes and new features of every version of our products.
Analog/Mixed-Signal Simulation and SPICE Device Modeling |
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|---|---|---|
| Product | Description | Version |
| SmartSpice | Parallel SPICE simulator | 4.32.4.R |
| SmartSpice Pro | Fast Circuit Simulator | 4.32.4.R |
| SmartSpice RF | Frequency and Time Domain RF Circuit Simulator | 4.32.4.R |
| Harmony | Analog/digital mixed-signal simulation solution | 4.16.17.R |
| SmartView | Waveform viewer and simulation analysis | 2.34.7.R |
| Utmost IV | Device characterization and SPICE modeling | 2.7.1.R |
| TechModeler | Device modeling for new technologies using only device behavior | 2018.1.0.R |
| Spayn | Statistical parameter and yield analysis tool for models and tests | 2.12.4.R |
Custom IC CAD |
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| Product | Description | Version |
|---|---|---|
| Gateway | Hierarchical schematic editor | 3.6.26.R |
| Expert | Hierarchical IC layout editor | 4.18.9.R |
| Guardian | Physical verification of layout networks with DRC/LVS | 4.10.16.R |
| Hipex | Full-chip parasitic extraction | 3.6.10.R |
Digital CAD |
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| Product | Description | Version |
|---|---|---|
| Silos | Verilog simulator | 4.16.17.R |
| HyperFault | Verilog IEEE-1364-2001 compliant fault simulator | 4.16.17.R |
| AccuCell | Cell characterization and modeling | 3.0.10.R |
| AccuCore | Block characterization, modeling and STA | 3.0.7.R |
| Spider | Netlist-to-GDSII place-and-route design flow | 1.8.2.R |
Parasitic Extraction |
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| Product | Description | Version |
|---|---|---|
| Clever | RC extractor for realistic 3D structures | 3.11.20.R |
| Exact | Full-chip LPE rule file generator | 2.20.3.R |
| Quest | 3D RF passive device modeling | 2.0.10.R |
Power Integrity Signoff |
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| Product | Description | Version |
|---|---|---|
| Invar | EM/IR, thermal reliability and power integrity analysis | 1.14.0 |
Extracted Netlist Analysis and Reduction |
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| Product | Description | Version |
|---|---|---|
| JivaroA | Extracted Netlist Analysis and Reduction | 5.8.39 |
| JivaroD | Extracted Netlist Analysis and Reduction | 5.8.87 |
TCAD |
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| Product | Description | Version |
|---|---|---|
| Victory Process | 3D process and stress simulator | 7.22.3 |
| Victory Device | 3D device simulator | 1.12.1 |
| Victory Mesh | Mesh integration between process and device or interconnect tools | 1.0.5 |
| Athena | 1D and 2D process and stress simulator | 5.22.1 |
| Atlas | Device simulation of material-based devices | 5.26.1 |
| Virtual Wafer Fab | Perform Design of Experiments (DOE) and optimization experiments | 2.12.10 |
| DeckBuild | Create, edit and run TCAD simulation input files | 4.6.7 |
| DevEdit | Ceates and edit mesh structures for 2D or 3D simulators | 2.8.26 |
| MaskViews | Layout editor for GDS2 or Silvaco’s layout format | 3.2.19.R |
| TonyPlot | Visualization tool for 1D and 2D TCAD structures | 3.10.16 |
| TonyPlot 3D | Visualization tool for 3D data from TCAD and parasitic extraction | 3.10.24.R |
| Radiant | Design software for optoelectronic thin film devices | 1.2.2.R |
Variation Aware-Design |
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| Product | Description | Version |
|---|---|---|
| VarMan | Variation-aware design solution | 2018.1.24.R |