Emptying The Storage Well Using Quasi Fermi Levels

ccdex02.in : Emptying The Storage Well Using Quasi Fermi Levels

Requires: SSuprem 4/S-Pisces/Luminous
Minimum Versions: Athena 5.22.3.R, Atlas 5.28.1.R

In this example a CCD structure is constructed using the Athena process simulator. This structure is passed to Atlas for electrical testing. The input file tests consist of three portions:

  • Construction of a CCD device
  • Emptying the storage well of carriers by directly setting the quasi-fermi levels
  • Illuminating the CCD with a light source and measuring the generated carriers

This example differs from the previous one in that no drain contact is used . The emptying of the well is performed by setting the quasi-fermi level of the n- active region directly.

The structure of this CCD is two polysilicon gates on top of silicon separated by a nitride/oxide insulator layer. The right hand gate will be used to collect the charge and the left hand gate will confine this charge under the right-hand gate.

At the start of the input file is the Athena process to produce the structure as described for the previous example. Electrodes are defined in Athena and the extract statement is used to measure the junction depth of the n- active layer.

In the Atlas simulation the material and models definition is similar to the previous example. The CVT surface transport model is not needed as this simulation does not include charge transfer.

The key technique demonstrated by this example is the use of setting the quasi fermi levels directly in Atlas. To set the quasi fermi levels for electrons the parameter n.bias is used. For this to work, it is necessary to use a zero carrier solution. The setting of method carriers=0 specifies a zero carrier solution, and only Poisson's equation for potential is solved.

Using 'n.bias' the electron quasi fermi level is set to +20V. This is a non equilibrium condition so the only way to use the solution of the continuity equations is to observe the electron concentration is in transient mode. Atlas is switched to solve for electron and holes using method carriers=2 . A short transient simulation then is performed and a structure file is saved. Plotting electron concentration in this structure file shows the CCD storage well to be depleted of electrons. An extract statement is used to quantify this.

In this CCD biasing scheme the storage node to the left is biased to +12V and the containment node to the left is biased at -8V. This ensures that charges generated under the storage gate are collected there.

In the final stage of the input file the CCD storage node is illuminated. The light beam is defined in the BEAM statement to be normally incident from the top, with an origin of (6.85,-1), width 4um and wavelength 800nm. All reflections, refraction and absorption in the layers of the structure are simulated by Atlas.

A transient illumination is defined lasting 1us. At the end of this time the amount of electrons trapped in the CCD can be measured using the extract statement.

To load and run this example, select the Load button in DeckBuild > Examples. This will copy the input file and any support files to your current working directory. Select the Run button in DeckBuild to execute the example.