Passivated Device : Passivated Device

Requires: S-Pisces/TFT
Minimum Versions: Atlas 5.24.1.R

This file performs Id/Vgs simulation of a TFT device with material properties corresponding to passivated polysilicon material. The example shows:

  • Structure formation using Atlas syntax
  • Material and model settings for passivated polysilicon
  • Forward Id/Vgs characteristics

The key command in TFT simulation is the defect statement. It is used to define a continuous density of trap states in the silicon and the relevant trapping cross-sections.

The Id/Vgs ramping is performed in a similar manner to the threshold voltage tests for MOS devices described in the MOS example. Results from this example can be compared with the un-passivated polysilicon device.

A more detailed description of TFT material settings is given in the Forward/Reverse Gate Voltage Characteristic example.

This corresponds to a passivated polysilicon material.

To load and run this example, select the Load button in DeckBuild > Examples. This will copy the input file and any support files to your current working directory. Select the Run button in DeckBuild to execute the example.