SEU in Memory Cell Transistor

radex06.in : SEU in Memory Cell Transistor

Requires: DevEdit 3D/Device 3D
Minimum Versions: Atlas 5.24.1.R

This example demonstrates SEU in a MOSFET with an external resistor and capacitor emulating a RAM cell. The example shows:

  • Formation of structure in DevEdit 3D
  • Parameterized structural and doping parameters
  • Automatic interface from DevEdit 3D to Device 3D
  • Setting of external resistor and capacitor on the drain contact
  • Definition of the SEU pulse
  • DC simulation to bias MOSFET in initial cell condition
  • Transient simulation of SEU strike
  • Analysis of voltage drop at the drain contact

To load and run this example, select the Load button in DeckBuild > Examples. This will copy the input file and any support files to your current working directory. Select the Run button in DeckBuild to execute the example.