IBC-SHJ Optimization

solarex18.in : IBC-SHJ Optimization

Requires: Blaze/Luminous
Minimum Versions: Atlas 5.28.1.R

References:

D.Munos et al. INES-CEA, "Key features of highly efficient a-Si:Hc-Si heterojunction solar cells" 7th Workshop on the future Direcftion of Photovoltaics )by JSPS 175th committee), march, 2011

D. Diouf, J.-P. Kleider, and C. Longeaud, Two-Dimensional Simulations of interdigitated ack Contact Silicon Heterojunctions Solar Cells, Chapter 15 of the book Physics and Technology of Amorphous-Crystalline Silicon Heterostructure Solar Cells, Springer 2011.

M.Lu et al "Optimizationn of interdigital back contact silicon solar cells by two-dimensional numerical simulation" IEEE 2009

This example demonstrates 2D simulation and optimization of a n-type Interdigitated Back Contact Silicon Heterojunction (IBC-SHJ) solar cell. Combination of amorphous silicon/crystalline silicon heterojunction and interdigitated back contact are very promising for high efficiency one junction solar cell.

The solar cell structure consists from top to bottom of a n-type c-Si substrate, an intrinsic a-Si buffer layer and interdigitated strips of p and n-type a-Si.

For a-Si layers, critical parameters like band gap, doping and defect distribution are defined in the input deck.

For c-Si/a-Si interfaces at the back surface a thermionic emission model was used. For even more realistic modeling of this interface we have introduced defect states at the hetero-interface by putting a very thin defective layer of c-Si.

Fermi model, Recombination models (i.e srh, auger and surface recombination) Drift Diffusion model with quantum correction were used to simulate IV characteristic of the solar cell under front surface illumination.

A complete parametrized input deck, including geometry and mesh, was created not only to optimize simulation time and accuracy but also for solar cell optimization purpose.

In this example 4 different parameters were varied to optimize the solar cell efficiency. These parameters are intrinsic a-Si thickness, n-stripe and p-strip width and gap width.

It was observed experimentally observed that an intrinsic a-Si layer increases Voc and Jsc but also decreases FF and leads to a "S" shape IV curve. Simulation results confirm the reduction of FF and "S" shape IV curve, as well as the increase of Voc when the thickness of the intrinsic a-Si layer increases, leading to an optimum efficiency of around 10nm for the intrinsic a-Si layer.

n-stripe, p-stripe and gap width were also optimized. Simulation results show that Jsc decreases when n-stripe width and gap width increases. As a consequence n-stripe and gap width have to be choosen as narrow as possible. It is interesting to notice that Jsc increases and FF decreases when p-stripe increases. The different evolution of Jsc anf FF leads to an optimum for the efficiency of around 1mm for p-stripe width.

To load and run this example, select the Load button in DeckBuild > Examples. This will copy the input file and any support files to your current working directory. Select the Run button in DeckBuild to execute the example.