2D Analysis of PD-SOI MOSFET and FET-Stack for RF CMOS Applications

soiex14.in : 2D Analysis of PD-SOI MOSFET and FET-Stack for RF CMOS Applications

Requires: Victory Process - Victory Device
Minimum Versions: Victory Process 7.30.4.R, Victory Mesh 1.4.6.R, Victory Device 1.14.1.R

This example demonstrates PD-SOI simulation using a 2D TCAD model, which is much faster and more efficient than using a 3D model (demonstrated in the previous soiex13.in example). A device layout (e.g. a GDSII file) can still be used for building a 2D TCAD model, but in this case, we use just a 2D cross-section along one cut-line across the layout. Here we generate a 2D model of 180nm PD-SOI NMOSFET from the existing 3D process flow in the previous soiex11.in example.

2D modeling is most appropriate for simulating floating-body PD-SOI MOSFETs without body contacts outside the channel. The SOI body-tie effects can still be quickly simulated and investigated using a 2D TCAD model if we apply an internal (artificial) contact at the bottom of the SOI body, just for analysis purposes. This is also demonstrated in this example.

A background and more detailed description can be found in the article:

[1] "Optimization of PD-SOI CMOS Process and Devices for RF Applications" (Silvaco Simulation Standard, Vol. 28, No. 1, 2018) .

RF SOI-CMOS is an important technology used in wireless applications such as tuners and power amplifiers, which can involve switching high power levels at high frequencies. In this example, the key design parameters for RF-CMOS are computed, which include:

  • "on-resistance" (Ron) , mainly related to the channel resistance of a FET;
  • "off-capacitance" (Coff) , associated with isolation between ports of a switch. Coff is a combination of a number of linear (interconnects) and nonlinear (gate, gate-to-source/drain, junctions, buried oxide) capacitances;
  • breakdown voltage (BV).

Ron*Coff is a key figure-of-merit for RF switch application. MOSFET channel length reduction along with necessary adjustments to doping profile can improve Ron*Coff, while achieving the required BV value.

To be able to handle high voltage levels (>30V), it is necessary to stack multiple FETs to form a switch arm. Due to gate and substrate losses, the voltage across FETs within an arm can vary significantly. The amount of imbalance increases rapidly with the stack height (stack height = number of FETs in a switch arm). Device design needs to take into consideration this imbalance, and this examples includes an analysis of a FET-stack too.

2D TCAD computation of all the above parameters is demonstrated in this example.

2D Advanced Process Simulation of a PD-SOI MOSFET

First, Victory Process tool is used to build the device structure, by advanced, physics-based simulations. The simulated PD-SOI process and devices are described in more detail in the previous soiex13.in example.

2D Device Simulations

Then, a number of different device characteristics are simulated using Victory Device simulator, which include:

  • Specification of materials, models, and simulation parameters
  • Simulation of steady-state Id-Vg characteristics (which allow to determine Vth and DIBL), Id-Vd characteristics (which allow to determine Ron), and breakdown voltage (BV) characteristics
  • Computation of small-signal (AC) capacitance-voltage (C-V) characteristics, which allow to determine Coff
  • Comparison of Id-Vd characteristics of a floating-body and body-tied NMOSFET
  • Large-signal transient simulation of an RF waveform (sinusoidal, 1GHz) of a stack of 4 FETs, to determine the voltage distribution (imbalance) across the FETs within the switch arm (stack)
  • Display of the results in TonyPlot

First, the initial solution is obtained (for zero bias). Then, the Id-Vg transfer characteristics are computed, for selected Vds voltages, from which the threshold voltage (Vth) can be extracted.

Next, the Breakdown I-V characteristic of the 180nm PD-SOI floating-body MOSFET is computed, for the gate bias Vg = 0 V.

Then, small-signal (AC) 2D TCAD simulations are performed using Victory Device, to obtain C-V characteristics of all the intrinsic capacitances of the MOSFET device. In this example, we demonstrate computation of the Capacitances vs. Gate Voltage (C-Vg) characteristics, which allows to determine the components of Coff (see [1]).

Next, a comparison of Id-Vd characteristics of a floating-body and body-tied NMOSFET is done, by inserting an additional (artificial) contact at the bottom of the P-body of the NMOSFET, just for the analysis purpose.

Finally, the large-signal transient simulation of an RF waveform (sinusoidal, 1GHz) of a stack of 4 FETs is performed, to determine the voltage distribution (imbalance) across the stack of multiple FETs connected in series.

The I-V and C-V curves are plotted using the Silvaco TonyPlot tool.

To load and run this example, select the Load button in DeckBuild > Examples. This will copy the input file and any support files to your current working directory. Select the Run button in DeckBuild to execute the example.