Drain/Gate Overlap Capacitance

mos2ex09.in : Drain/Gate Overlap Capacitance

Requires: SSuprem 4/DevEdit/S-Pisces
Minimum Versions: Athena 5.22.3.R, Atlas 5.24.1.R

This example demonstrates the extraction of the gate overlap capacitance for an LDD MOSFET structure. The example shows:

  • Construction of an LDD MOSFET in Athena
  • Regrid of the structure in DEVEDIT
  • Gate/drain overlap capacitance extraction using AC analysis

A LDD NMOS device is constructed, remeshed and loaded into Atlas. The process simulation, interface to DEVEDIT and initial setup in Atlas are described in the previous section under MOS examples.

One requirement for AC simulation is that a two carrier solution must be specified. This is set with method carriers=2 . After the initial solution, a solution at a gate bias of -2 volts is obtained using the local initial guess. The local method is convenient when taking large voltage steps, but it assumes no current flow.

Next, the log statement is used to specify a file for saving the results of the gate ramp. Then, the gate is swept from -2 volts to 2 volts in 0.2 volt increments. At each static solution of gate bias the small signal AC response is solved at a frequency of 1 MHz. These results are saved in the log file. Finally the overlap capacitance as a function of gate bias is plotted using TonyPlot. In the list of XY graph variables in the TonyPlot DISPLAY menu, the capacitances and conductances are listed as: C electrode_name_1 > electrode_name_2 . This means the capacitance between these two electrodes. A similar construction is used with 'G' for conductance between two electrodes. When the two electrode names are the same, the magnitude of this value is the total capacitance on this electrode.

To load and run this example, select the Load button in DeckBuild > Examples. This will copy the input file and any support files to your current working directory. Select the Run button in DeckBuild to execute the example.