Hot Electron Reliability : Hot Electron Reliability

Requires: S-Pisces/C-Interpreter
Minimum Versions: Atlas 5.24.1.R

This is a demonstration of the hot carrier reliability feature of Atlas. A PMOS transistor is stressed at high voltages and a threshold voltage shift observed. The simulation shows:

  • Formation of PMOS transistor using Atlas syntax
  • Id/Vgs test
  • High voltage stress for 1000 seconds
  • Id/Vgs tests of devices at various stress times.

The example file consists of five separate Atlas runs each starting with the statement go atlas . The first run uses the Atlas syntax to construct the geometry, mesh and doping of a PMOS transistor. The doping is specified using gaussian functions. The mesh file saved by this run is loaded into the next run.

The second Atlas run sets commands to perform an Id/Vgs simulation to observe the threshold voltage and gain. A more complete description of extracting PMOS threshold can be found in the MOS examples section.

The device degradation modeling is performed in the third run. First, the structure is loaded and the correct workfunction and interface fixed charge are set. On the models statement, the standard mobility and recombination models are specified. The parameters hei devdeg.e are also set. hei turns on the hot electron injection model for gate current. The devdeg.e parameter sets that the gate current is used to calculate device degradation. The degradation parameter is used to specify the interface state density and the electron trapping cross section, sigmae. The density of interface states as a function of position is defined here using a C-INTERPRETER routine. The external file mos2ex02_devdeg.nta is used in this example. This file will be copied to your current working directory if you press 'Load'. This file contains a C language description of the density of acceptor-like traps at the oxide/silicon interface. Use of the C-INTERPRETER allows complete flexibility in specifying the position of the traps.

The stressing conditions are Vds=-6.0V and Vgs=-1.5V. The device is biased to these voltages in DC mode. Atlas is then switched to a transient solution. Since the time of this transient is very long compared with the transit time of carriers a faster transient solution method can be selected using method quasistatic .

The transient simulation is set to run for 1000s. At various intervals, data is saved to solution files whose prefix is set to 'mosex02.str'. The statement output devdeg is required to save the interface trap occupancy to these solution files. These files will be the initial starting points of the subsequent Id/Vgs runs.

The fourth and fifth runs are just repetitions of the second one. They perform the Id/Vgs test to observe threshold voltage and gain. However the important difference is the the file loaded in the mesh statement is the output files saved during the transient stress.

The Id/Vgs curves from the second, fourth and fifth runs can be overlaid in TonyPlot to show the threshold voltage shift caused by the hot carriers trapped at the interface.

To load and run this example, select the Load button in DeckBuild > Examples. This will copy the input file and any support files to your current working directory. Select the Run button in DeckBuild to execute the example.