3D Process and Device Simulation of a Split-Gate Trench UMOSFET

powerex23.in : 3D Process and Device Simulation of a Split-Gate Trench UMOSFET

Requires: Victory Process - Victory Device
Minimum Versions: Victory Process 7.30.4.R, Victory Mesh 1.4.6.R, Victory Device 1.14.1.R

By default Victory Process and Victory Device run on just one processor. To ensure better performance on your computer, the following simulation condition simflags="-P all" could be specified in the go line starting Victory Process or Device. This means that all processors available will be used. If you want to use a smaller number of processors you can substitute "all" with a desired number, e.g. simflags="-P 4".

This example demonstrates advanced 3D process and device simulations for a U-shaped trench power MOSFET called Split-Gate Trench UMOSFET . It is related to the Silvaco Simulation Standard (Vol.28, No.1, 2018) article "Advanced Process and Device 3D TCAD Simulation of Split-Gate Trench UMOSFET".

For the low to medium voltage ranges (12 V ~ 250 V), the split gate structures have become prevalent in the power MOSFET technologies. They allow to achieve the best trade-off between the breakdown voltage (BV) and specific on-state resistance (Rsp) for the vertical discrete power MOSFETs. Most of these solutions are based on the RESURF (Reduced Surface Field) action of Split-Gate Resurf Stepped Oxide (SG-RSO) along the drift region.

In the split-gate (SG) version of UMOSFET the bottom part of the gate, called Field Plate or Split Gate, is isolated from the gate so that the upper part next to the channel (the actual gate) and the lower part next to the drift region (the field plate) are connected independently, the field plate being usually connected to the source (grounded). This results in a drastic decrease in the capacitance between the gate and the drain (Cgd) while still maintaining the RESURF effect induced by the field plate.

3D Advanced Process Simulation of a Split-Gate UMOSFET

In the first part of this example, Victory Process tool is used to build the device structure, by advanced, physics-based simulations of several process steps commonly used for modern Split-Gate UMOS fabrication. The simulated process steps include: a) formation of a deep trench with rounded bottom, by a combination of Dry and Wet Etch steps, b) shield (thick) oxide growth, c) shield poly (field plate) deposition, d) inter-poly oxide deposition and etch back to obtain the thinner gate-oxide, e) gate poly deposition and etch back, f) core contact etching and deposition of the contact plug and metallization (for the Source contact).

3D Numerical Mesh

Next, the Silvaco new Victory Mesh tool is used for appropriate 3D meshing of the structure. Based on the complex shapes of materials (boundaries) and doping profiles, a 3D Delaunay mesh is generated to appropriately resolve all the complex 3D geometrical features and the electrical intricacies of the device.

3D Device Simulations

Then, a number of different device characteristics are simulated using Victory Device simulator, which include:

  • Specification of materials, models, and simulation parameters
  • Simulation of steady-state Id-Vg, gm-Vg, Id-Vd, and breakdown voltage (BV) characteristics
  • Computation of small-signal (AC) capacitance-voltage (C-V) characteristics
  • Display of the results in TonyPlot

First, the initial solution is obtained (for zero bias). Then, the Id-Vg transfer characteristics are computed, from which the threshold voltage (Vth) and the transconductance gm-Vg characteristics can be extracted.

Next, the Id-Vd output characteristics are computed, for a selected Vgs bias voltage.

Then, the Breakdown I-V characteristic of the Split-Gate UMOSFET is computed, for the gate bias Vg = 0 V.

The I-V curves are plotted using the Silvaco TonyPlot tool. The transconductance gm (dId/dVg) curve can be plotted using Display > Functions... feature in TonyPlot.

Small-signal (AC) Capacitance-Voltage (C-V) Characteristics

As next step, small-signal (AC) 3D TCAD simulations are performed using Victory Device, to obtain C-V characteristics of all the intrinsic capacitances of the UMOS device. In this example, we demonstrate computation of the Capacitances vs. Drain Voltage (C-Vd) characteristics, which are often important for power MOSFETs.

To load and run this example, select the Load button in DeckBuild > Examples. This will copy the input file and any support files to your current working directory. Select the Run button in DeckBuild to execute the example.