3D BiGT On-State Characteristics as a Function of the Anode Shorts Layout Design

powerex16.in : 3D BiGT On-State Characteristics as a Function of the Anode Shorts Layout Design

Requires: Victory Process/Victory Device
Minimum Versions: Victory Process 7.30.4.R, Victory Mesh 1.4.6.R, Victory Device 1.12.2.R

By default Victory Process and Device run on just one processor. To ensure better perfomance on your computer the following simulation condition simflags="-P all" could be specidied in the go line starting Victory Process or Device. This means that all processors available will be used. If you want to use a smaller number of processors you can substitute "all" with a desired number, e.g. simflags="-P 4".

This example compares the on-state IGBT mode performance of the Bi-mode Insulated Gate Transistor (BiGT) [1] with two different anode shorts stripe designs: parallel stripes S1 and radial stripes S2. Both structures S1 and S2 have the same widths of the n+ shorts and the p+ anode segments of 100 um and 400um, respectively.

The 3D BiGT structures are generated by Victory Process. The process simulation starts with a 2.5um-thick anode/collector region (INIT SILICON DEPTH = 2.5) comprising an area of 0.5mm by 4 mm (FROM = "0, 0" TO = "4000, 500"), in which the total height of the final structure above the anode/collector region is assumed to be less than or equal to 200 um. A SPECIFYMASKPOLY statement defines a polygonal mask that corresponds to each layout design, while a combination of the MASK and the DOPING statement allows a uniform doping to be introduced directly into a particular portion of the device volume. Thus, the desired patterns can be produced in the anode/collector region. For ease of simulation, a 1 µm-thick heavily doped n-type layer of silicon (DEPOSIT SILICON THICKNESS = 1 PHOSPHORUS = 1E19) is put in place of MOS cells on the emitter side of the BiGT to render the on-state IGBT mode of the BiGT.

Victory Device performs 3D device simulations in transient mode to detect possible snapback effects in the BiGT on-state I-V characteristics. Parallel-electric-field, inversion-layer, temperature, and doping-dependent mobility models (CVT) as well as the Shockley-Read-Hall (SRH) recombination model are used during 3D simulation. The collector current is ramped up from 0 A to 30 A at a constant rate of 1 A/s, which can be done by first specifying the current boundary condition on the collector contact with the help of the CONTACT NAME=collector CURRENT command, and then giving a value to the ICOLLECTOR, RAMPTIME, TSTEP, and TSTOP parameters on the SOLVE statement. With the TOL.TIME=1 parameter on the METHOD statement, the tolerance for a local truncation error used by an adaptive time-stepping algorithm is set to 1 instead of the default value of 5 × 10-3. Simultaneously, by means of the NORM.SCALING.LOCAL and NEWTON parameters on the METHOD statement, the RHS norms and their tolerances are scaled locally and the Newton solver is resorted to for transient simulations, respectively. The ATRAP=0.1 parameter on the METHOD statement instructs Victory Device to multiply the time-step by a factor of 0.1 once the Newton solver fails to converge. During the transient ramp-up of collector current, the SAVE statement is repeatedly employed to save carrier density data to structure files at various current values for visualization in Tonyplot.

I-V curve of design S1 differs from that of design S2 in the occurrence of a number of voltage snapbacks. Furthermore, the S1 design exhibits a higher on-state voltage drop than the S2 design. A glance at the electron distribution in a cut plane defined along the z-axis at z = -40 um at three different values of collector current reveals smooth transition of the BiGT with design S2 into full conduction as a result of the spread of electrons along the entire device length at a relatively low current. In the case of design S1, on the contrary, electrons spread over the whole device in a step-like manner, causing th voltage to snapback at each progressive stage of the electron spread over the p+ anode segments.

To load and run this example, select the Load button in DeckBuild. This will copy the input file and any support files to your current working directory. Select the run button to execute the example.

References: [1] L. Storasta, M. Rahimo, M. Bellini, A. Kopta, U. R. Vemulapati, and N. Kaminski, "The Radial Layout Design Concept for the Bi-mode Insulated Gate Transistor " Proc. ISPSD11, pp. 56-59, 2011.