Vertical DMOS Gate Charging Simulation

powerex11.in : Vertical DMOS Gate Charging Simulation

Requires: SSuprem 4/DevEdit/MixedMode
Minimum Versions: Athena 5.22.3.R, Victory Device 1.14.1.R or Atlas 5.28.1.R

In modern power devices the total power loss comprises both a conductance power loss component and a capacitive loss component. As the cell pitch decreases, the conduction loss will decrease while the capacitive loss will increase. Therefore for small cell pitch the capacitive power loss may be the dominant component in the total power loss in the device. The need is now clear for a method that will allow analysis of the capacitive component of the power loss. One technique for doing this in a DMOS device is to analyze the gate charging time. This example illustrates a technique whereby the gate charging time for a vertical DMOS structure may be simulated, and the gate charge (Qg) required for switching the MOSFET can be determined.

The example contains the following parts:

  • Process simulation to create the vertical DMOS
  • The SPICE-like command syntax for simulating MixedMode circuits
  • Steady state analysis that defines the DC operating point
  • Time domain analysis that illustrates gate charging

The Device/MixedMode simulation in this example (the last three bullets above) can be run by either Victory Device or Atlas simulator, just by changing the solver name in the command go victorydevice into go atlas . It shows that both Victory Device and Atlas device simulators can be fully compatible in terms of input commands, producing same results, and allowing easy transition between Atlas and Victory Device.

The first section uses Athena/SSuprem 4 to build a vertical DMOS power device. This section is identical to that used in the example powerex02.in which is described earlier in this power device section. For information on the process description please refer to this prior example.

After the process simulation, the structure is remeshed with DevEdit using the command go devedit .

At this point the solution only contains quantities from the process simulator, so only impurity values are available as remeshing criteria. These are selected with the commands:

imp.refine imp="Net Doping" scale=log transition=1e+10 sensitivity=2 imp.refine min.spacing=0.2

In addition to the doping profile, DevEdit is used to obtain a denser mesh within the channel region underneath the gate. This is performed in two stages with the commands:

constr.mesh id=1 x1=2.5 y1=0 x2=1e+06 y2=0.5 default max.height=0.1 max.width=2

constr.mesh id=2 x1=2 y1=0 x2=4.5 y2=0.5 default max.height=0.1 max.width=0.2

The mesh is then created using the DevEdit command

Mesh Mode=MeshBuild

Once the mesh has been designed for the electrical analysis it is passed on to the device simulator. This analysis is conducted using the mixed device and circuit simulator MixedMode. First, a steady-state simulation of the power circuit is performed.

The .begin and .end statements indicate the beginning and end of the MixedMode syntax. The MixedMode commands are similar to those used in SmartSpice. Circuit components, topology, and analysis are defined within these statements. In general, the circuit component definition consists of three parts: the type of component, the lead or terminal node assignments, and the component value or model name.

For example, the first component definition in this simulation is an independent current source defined by iin between the circuit nodes 0 and GG . The final value of 0 indicates that the initial current source value is 0 Amps. The remaining circuit components are a resistor Rg , another independent current source iout a compact diode model dout and a voltage source vdd .

The amos statement specifies a device to be analyzed by Atlas. The a part of the amos command specifies that this is a TCAD device statement. The mos portion simply defines the device name. The option infile= indicates which device structure file is to be used. The .nodeset statement defines the initial values for node voltages. The .dc statement indicates that a dc ramp is applied to the source iout . Additionally, the .options command specifies the numerical method used in the simulation. The .save outfile= statement saves the final solution to the indicated file, once the .dc ramp is complete.

Other command line options exist. Please refer to the MixedMode section of the Atlas or Victory Device user's manual for a complete list.

To completely specify the simulation, the physical models used by Atlas/Victory Device must be specified. The models statement is used to turn on the appropriate transport models. This set includes: cvt - mobility model for MOSFETs, srh - Shockley-Read-Hall recombination, auger - recombination accounting for high level injection effects, and bgn - band gap narrowing. Refer to the user's manual for a description of these models. Finally, an impact ionization model is enabled using the impact statement with the selb option. This specifies that the Selberherr impact ionization model is to be used.

The next step is the transient MixedMode analysis, which is specified in a similar manner as the steady-state MixedMode simulation described above. The charging effect of the gate is simulated by applying a long current pulse of constant value to the gate, by the independent current source iin . The .tran statement is used to specify the initial time step and total duration of the transient analysis. In addition, the .log statement saves all the transient simulation results over the time interval specified.

TonyPlot is used to plot the transient response of the device and circuit. The Gate Charge, Qg (in Coulombs) can be calculated and plotted in TonyPlot using Display > Functions... feature.

To load and run this example, select the Load button in DeckBuild > Examples. This will copy the input file and any support files to your current working directory. Select the Run button in DeckBuild to execute the example.