Gate Length Scaling

mos1ex15.in : Gate Length Scaling

Requires: SSuprem 4/S-Pisces
Minimum Versions: Athena 5.22.3.R, Atlas 5.28.1.R

This is an Athena/Atlas interface example similar to the first example in this section. It demonstrates the setting of gate length through parameter substitution.

In this example an NMOS transistors length is defined with a set statement around the poly etch stage in the simulation. The set statement defines a variable used in a subsequent stretch statement to define the half length of the transistor.

Importantly, the variable $cd is also used to place the name of the drain electrode in the subsequent electrode statement. This simplifies the position definition of the drain electrode.

Note the use of the right statement in the stretch command. This makes sure that the coordinate system of the stretched device remains unchanged from the original making sure that the left hand side of the structure is in the same place as before. Both right|left flags are available.

To load and run this example, select the Load button in DeckBuild > Examples. This will copy the input file and any support files to your current working directory. Select the Run button in DeckBuild to execute the example.